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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id p16-20020a170903249000b0017f864355aasm416947plw.164.2022.10.06.21.03.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Oct 2022 21:03:56 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, msebor@gcc.gnu.org, jakub@gcc.gnu.org, rguenth@gcc.gnu.org, koen.zandberg@inria.fr, andy.chiu@sifive.com, guoren@kernel.org, greentime.hu@sifive.com, palmer@dabbelt.com Subject: [PATCH] PR middle-end/88345: Honor -falign-functions=N even optimized for size. Date: Fri, 7 Oct 2022 12:03:25 +0800 Message-Id: <20221007040325.21276-1-kito.cheng@sifive.com> X-Mailer: git-send-email 2.37.2 MIME-Version: 1.0 X-Spam-Status: No, score=-13.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=unavailable autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Monk Chiang Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Monk Chiang Currnetly setting of -falign-functions=N will be ignored if the function is optimized for size or marked as cold function. However function alignment requirement is needed even optimized for size in some situations, RISC-V target is an example, RISC-V kernel implement patchable function that require function must be align to at least 4 bytes for atomicly patch the function prologue. Here is 4 way to fix that: 1. Fix -falign-functions=N, let it work as expect on -Os and all cold functions, which is this patch. 2. Force align to 4 byte if -fpatchable-function-entry is given by adjust RISC-V's FUNCTION_BOUNDARY. 3. Adjust RISC-V's FUNCTION_BOUNDARY to let it honor to -falign-functions=N. 4. Adding a -malign-functions=N for RISC-V...which x86 already deprecated that. And this patch is the first approach. gcc/ChangeLog: PR middle-end/88345 * varasm.cc (assemble_start_function): Adjust function align even optimized for size. * doc/invoke.texi (Os): Remove -falign-functions= from the exclusion list of -Os. gcc/testsuite/ChangeLog: PR middle-end/88345 * gcc.target/i386/pr88345-1.c: New. * gcc.target/i386/pr88345-2.c: Ditto. * gcc.target/riscv/pr88345-1.c: Ditto. * gcc.target/riscv/pr88345-2.c: Ditto. Reviewed-by: Palmer Dabbelt --- gcc/doc/invoke.texi | 2 +- gcc/testsuite/gcc.target/i386/pr88345-1.c | 5 +++++ gcc/testsuite/gcc.target/i386/pr88345-2.c | 5 +++++ gcc/testsuite/gcc.target/riscv/pr88345-1.c | 5 +++++ gcc/testsuite/gcc.target/riscv/pr88345-2.c | 5 +++++ gcc/varasm.cc | 3 +-- 6 files changed, 22 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr88345-1.c create mode 100644 gcc/testsuite/gcc.target/i386/pr88345-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr88345-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/pr88345-2.c diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index a2b0b9636f0..acf98c68825 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -11381,7 +11381,7 @@ results. This is the default. Optimize for size. @option{-Os} enables all @option{-O2} optimizations except those that often increase code size: -@gccoptlist{-falign-functions -falign-jumps @gol +@gccoptlist{-falign-jumps @gol -falign-labels -falign-loops @gol -fprefetch-loop-arrays -freorder-blocks-algorithm=stc} diff --git a/gcc/testsuite/gcc.target/i386/pr88345-1.c b/gcc/testsuite/gcc.target/i386/pr88345-1.c new file mode 100644 index 00000000000..226bb9ffc82 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr88345-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-falign-functions=128" } */ +/* { dg-final { scan-assembler-times "\.p2align\t7" 1 } } */ + +__attribute__((__cold__)) void a() {} diff --git a/gcc/testsuite/gcc.target/i386/pr88345-2.c b/gcc/testsuite/gcc.target/i386/pr88345-2.c new file mode 100644 index 00000000000..a7fc3b162dd --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr88345-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-falign-functions=128 -Os" } */ +/* { dg-final { scan-assembler-times "\.p2align\t7" 1 } } */ + +void a() {} diff --git a/gcc/testsuite/gcc.target/riscv/pr88345-1.c b/gcc/testsuite/gcc.target/riscv/pr88345-1.c new file mode 100644 index 00000000000..7d5afe683eb --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr88345-1.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-falign-functions=128" } */ +/* { dg-final { scan-assembler-times "\.align\t7" 1 } } */ + +__attribute__((__cold__)) void a() {} diff --git a/gcc/testsuite/gcc.target/riscv/pr88345-2.c b/gcc/testsuite/gcc.target/riscv/pr88345-2.c new file mode 100644 index 00000000000..d4fc89d86d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/pr88345-2.c @@ -0,0 +1,5 @@ +/* { dg-do compile } */ +/* { dg-options "-falign-functions=128 -Os" } */ +/* { dg-final { scan-assembler-times "\.align\t7" 1 } } */ + +void a() {} diff --git a/gcc/varasm.cc b/gcc/varasm.cc index 423f3f91af8..4001648b214 100644 --- a/gcc/varasm.cc +++ b/gcc/varasm.cc @@ -1923,8 +1923,7 @@ assemble_start_function (tree decl, const char *fnname) Note that we still need to align to DECL_ALIGN, as above, because ASM_OUTPUT_MAX_SKIP_ALIGN might not do any alignment at all. */ if (! DECL_USER_ALIGN (decl) - && align_functions.levels[0].log > align - && optimize_function_for_speed_p (cfun)) + && align_functions.levels[0].log > align) { #ifdef ASM_OUTPUT_MAX_SKIP_ALIGN int align_log = align_functions.levels[0].log;