testsuite: Sanitize fails for SP FPU on Arm
Commit Message
This patch stops reporting fails for Arm targets with single
precision floating point unit for types wider than 32 bits (the width
of float on arm-none-eabi).
As reported in PR102017, fenv is reported as supported in recent
versions of newlib. At the same time, for some Arm targets, the
implementation in libgcc does not support exceptions and thus, the
test fails with a call to abort().
gcc/testsuite/ChangeLog:
* gcc.dg/c2x-float-7.c: Invert the exception check for Arm
targets with SP FPU.
* gcc.dg/pr95115.c: Likewise.
* gcc.dg/torture/float32x-nan-floath.c: Likewise.
* gcc.dg/torture/float32x-nan.c: Likewise.
* gcc.dg/torture/float64-nan-floath.c: Likewise.
* gcc.dg/torture/float64-nan.c: Likewise.
* gcc.dg/torture/inf-compare-1.c: Likewise.
* gcc.dg/torture/inf-compare-2.c: Likewise.
* gcc.dg/torture/inf-compare-3.c: Likewise.
* gcc.dg/torture/inf-compare-4.c: Likewise.
Co-Authored-By: Yvan ROUX <yvan.roux@foss.st.com>
Signed-off-by: Torbjörn SVENSSON <torbjorn.svensson@foss.st.com>
---
gcc/testsuite/gcc.dg/c2x-float-7.c | 10 ++++++++++
gcc/testsuite/gcc.dg/pr95115.c | 5 +++++
gcc/testsuite/gcc.dg/torture/floatn-nan-floath.h | 5 +++++
gcc/testsuite/gcc.dg/torture/floatn-nan.h | 10 ++++++++++
gcc/testsuite/gcc.dg/torture/inf-compare-1.c | 5 +++++
gcc/testsuite/gcc.dg/torture/inf-compare-2.c | 5 +++++
gcc/testsuite/gcc.dg/torture/inf-compare-3.c | 5 +++++
gcc/testsuite/gcc.dg/torture/inf-compare-4.c | 5 +++++
8 files changed, 50 insertions(+)
Comments
On Thu, 22 Sep 2022, Torbjörn SVENSSON via Gcc-patches wrote:
> This patch stops reporting fails for Arm targets with single
> precision floating point unit for types wider than 32 bits (the width
> of float on arm-none-eabi).
>
> As reported in PR102017, fenv is reported as supported in recent
> versions of newlib. At the same time, for some Arm targets, the
> implementation in libgcc does not support exceptions and thus, the
> test fails with a call to abort().
It's definitely wrong to have this sort of Arm-specific conditional in
architecture-independent tests. Tests requiring floating-point exceptions
support should have an appropriate dg-require-effective-target; if that
dg-require-effective-target wrongly passes in certain configurations, fix
it (or e.g. add a new check_effective_target_fenv_exceptions_double to
verify that exceptions work for double, as opposed to the present
check_effective_target_fenv_exceptions which checks whether exceptions
work for float, and then adjust tests requiring exceptions for double to
use the new effective-target).
Hi Joseph,
On 2022-09-23 00:42, Joseph Myers wrote:
> On Thu, 22 Sep 2022, Torbjörn SVENSSON via Gcc-patches wrote:
>
>> This patch stops reporting fails for Arm targets with single
>> precision floating point unit for types wider than 32 bits (the width
>> of float on arm-none-eabi).
>>
>> As reported in PR102017, fenv is reported as supported in recent
>> versions of newlib. At the same time, for some Arm targets, the
>> implementation in libgcc does not support exceptions and thus, the
>> test fails with a call to abort().
>
> It's definitely wrong to have this sort of Arm-specific conditional in
> architecture-independent tests. Tests requiring floating-point exceptions
> support should have an appropriate dg-require-effective-target; if that
> dg-require-effective-target wrongly passes in certain configurations, fix
> it (or e.g. add a new check_effective_target_fenv_exceptions_double to
> verify that exceptions work for double, as opposed to the present
> check_effective_target_fenv_exceptions which checks whether exceptions
> work for float, and then adjust tests requiring exceptions for double to
> use the new effective-target).
>
Okay, thanks for your review.
I will split this test case into 3 files as for SP FPU, we would like to
verify that the exception handling for the float part work, but at the
same time we know that exception handling for double and long double
should not work.
Do you think it's preferable to have the double and long double should
be reported as UNSUPPORRTED, or as XFAIL for the SP FPU case?
@@ -39,11 +39,21 @@ main (void)
abort ();
feclearexcept (FE_ALL_EXCEPT);
d += d;
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (fetestexcept (FE_INVALID))
+#else
if (!fetestexcept (FE_INVALID))
+#endif
abort ();
feclearexcept (FE_ALL_EXCEPT);
ld += ld;
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (fetestexcept (FE_INVALID))
+#else
if (!fetestexcept (FE_INVALID))
+#endif
abort ();
exit (0);
}
@@ -19,7 +19,12 @@ main (void)
double r = x ();
if (!__builtin_isnan (r))
abort ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (fetestexcept (FE_INVALID))
+#else
if (!fetestexcept (FE_INVALID))
+#endif
abort ();
exit (0);
}
@@ -30,7 +30,12 @@ main (void)
{
volatile TYPE r;
r = nans_cst + nans_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (fetestexcept (FE_INVALID))
+#else
if (!fetestexcept (FE_INVALID))
+#endif
abort ();
exit (0);
}
@@ -30,10 +30,20 @@ main (void)
{
volatile TYPE r;
r = nan_cst + nan_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (!fetestexcept (FE_INVALID))
+#else
if (fetestexcept (FE_INVALID))
+#endif
abort ();
r = nans_cst + nans_cst;
+#if defined(__ARM_FP) && __ARM_FP == 4 && (EXT || WIDTH > 32)
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (fetestexcept (FE_INVALID))
+#else
if (!fetestexcept (FE_INVALID))
+#endif
abort ();
exit (0);
}
@@ -16,6 +16,11 @@ int
main (void)
{
i = x > __builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (i != 0 || fetestexcept (FE_INVALID))
+#else
if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
abort ();
}
@@ -16,6 +16,11 @@ int
main (void)
{
i = x < -__builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (i != 0 || fetestexcept (FE_INVALID))
+#else
if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
abort ();
}
@@ -16,6 +16,11 @@ int
main (void)
{
i = x <= __builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (i != 0 || fetestexcept (FE_INVALID))
+#else
if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
abort ();
}
@@ -16,6 +16,11 @@ int
main (void)
{
i = x >= -__builtin_inf ();
+#if defined(__ARM_FP) && __ARM_FP == 4
+ /* Arm with SP FPU does not support exceptions (see pr102017). */
+ if (i != 0 || fetestexcept (FE_INVALID))
+#else
if (i != 0 || !fetestexcept (FE_INVALID))
+#endif
abort ();
}