From patchwork Tue Aug 30 06:27:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 57160 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A72953AA800C for ; Tue, 30 Aug 2022 06:28:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgjp3.qq.com (smtpbgjp3.qq.com [54.92.39.34]) by sourceware.org (Postfix) with ESMTPS id F06A8385E00A for ; Tue, 30 Aug 2022 06:28:03 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org F06A8385E00A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp66t1661840874twbnbikk Received: from server1.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Aug 2022 14:27:53 +0800 (CST) X-QQ-SSF: 01400000000000C0I000000A0000000 X-QQ-FEAT: D6RqbDSxuq4Cud6Q73Dai6NLwRwSJDbMaRlgC6EppfKzNFzmujXIElDBBdRFZ aNFY0ef85MQT7dTE5rrYq5AVArFLScBOxrA9YMUMXG8kSIPOfOc3j9eYm9zipCljeMxzGnq bk/EnE9PCcHlo85Nuu0DsJYw25Oq6ET5Dp+b4cCF18d9AyfNKyHVipOwEbBQ+JAVMcFpDrV hVCh4eXfK62B3NlVxTb7Tf3aoCqgVXDrrPTb5fLiC51CwbkZdwk4unx/9pZ3iIF6uyQKYJ+ KiiZsWDrav68OzHeQigD95dxfXkbJsnXzNHvT6siyikU4nClTkEZI69piQFWJK2AdUmq96V 5v9coyjj46Zdem5ZPE+waimRRZnZz8hpc5etME9Od2ew4Bijaxo0aWYNt5aArl0iou9bKhl X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add RVV registers in TARGET_CONDITION_AL_REGISTER_USAGE Date: Tue, 30 Aug 2022 14:27:52 +0800 Message-Id: <20220830062752.94761-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, zhongjuzhe Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: zhongjuzhe gcc/ChangeLog: * config/riscv/riscv.cc (riscv_conditional_register_usage): Add RVV registers. --- gcc/config/riscv/riscv.cc | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 50de6a83cba..aebe3c0ab6b 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -5439,6 +5439,15 @@ riscv_conditional_register_usage (void) for (int regno = FP_REG_FIRST; regno <= FP_REG_LAST; regno++) call_used_regs[regno] = 1; } + + if (!TARGET_VECTOR) + { + for (int regno = V_REG_FIRST; regno <= V_REG_LAST; regno++) + fixed_regs[regno] = call_used_regs[regno] = 1; + + fixed_regs[VTYPE_REGNUM] = call_used_regs[VTYPE_REGNUM] = 1; + fixed_regs[VL_REGNUM] = call_used_regs[VL_REGNUM] = 1; + } } /* Return a register priority for hard reg REGNO. */