From patchwork Tue Aug 30 06:20:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "juzhe.zhong@rivai.ai" X-Patchwork-Id: 57159 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C73283842405 for ; Tue, 30 Aug 2022 06:21:07 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtpbgbr1.qq.com (smtpbgbr1.qq.com [54.207.19.206]) by sourceware.org (Postfix) with ESMTPS id 53579385141E for ; Tue, 30 Aug 2022 06:20:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 53579385141E Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=rivai.ai Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=rivai.ai X-QQ-mid: bizesmtp90t1661840430tsuhdnaf Received: from server1.localdomain ( [42.247.22.66]) by bizesmtp.qq.com (ESMTP) with id ; Tue, 30 Aug 2022 14:20:29 +0800 (CST) X-QQ-SSF: 01400000000000C0I000000A0000000 X-QQ-FEAT: Fc2LLDWeHZ8codLPs+AsHa1D8j1hgH6ZYYQeJ150OvcBtHKXQDI+R7gh5Kd2F kYZncnIOO+hQnqVhCs8PjszHYngH5Y4Uo2FNizIZHE7umJYEsb8SL5GstCL3JV2w2TK42Ea Uz5LlrMzG9IXJ0jc2CV+zDc5/qS1rWRMH/NO1ns2+c75nefuuqgEz/B1iDbKLbAlj6Yk2XC rNq/NmlHyy2J+jpL8s9yQ3PMGxMOiZA/6T1IA+jdmEAlFOucHIagqHDkSR5NjTewGtEhaIL +vVBlmeERc3gWR2c9neTT2WW2P0vLwvJC9oSn2ATOdxSY4AMfU1jNwCyI4owhA7meL+gJE4 NPue33AsXf1u5s2dv2goaSb20E/67fKaCCY5GmKYBU4b6Iafn+2KefcPoaWUtO0hw/AkStp X-QQ-GoodBg: 2 From: juzhe.zhong@rivai.ai To: gcc-patches@gcc.gnu.org Subject: [PATCH] RISC-V: Add csrr vlenb instruction. Date: Tue, 30 Aug 2022 14:20:27 +0800 Message-Id: <20220830062027.252003-1-juzhe.zhong@rivai.ai> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-QQ-SENDSIZE: 520 Feedback-ID: bizesmtp:rivai.ai:qybglogicsvr:qybglogicsvr7 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_MSPIKE_H2, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE, T_SPF_HELO_TEMPERROR, URIBL_BLACK autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kito.cheng@gmail.com, zhongjuzhe Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: zhongjuzhe gcc/ChangeLog: * config/riscv/riscv.cc (riscv_const_insns): Add cost of poly_int. (riscv_output_move): Add csrr vlenb assembly. * config/riscv/riscv.md (move_type): Add csrr vlenb type. (ext): New attribute. (ext_enabled): Ditto. (enabled): Ditto. --- gcc/config/riscv/riscv.cc | 13 +++++++ gcc/config/riscv/riscv.md | 79 ++++++++++++++++++++++++++++----------- 2 files changed, 70 insertions(+), 22 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index ef606f33983..50de6a83cba 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1136,6 +1136,12 @@ riscv_const_insns (rtx x) case LABEL_REF: return riscv_symbol_insns (riscv_classify_symbol (x)); + /* TODO: In RVV, we get CONST_POLY_INT by using csrr vlenb + instruction and several scalar shift or mult instructions, + it is so far unknown. We set it to 4 temporarily. */ + case CONST_POLY_INT: + return 4; + default: return 0; } @@ -2507,6 +2513,13 @@ riscv_output_move (rtx dest, rtx src) return "fld\t%0,%1"; } } + if (dest_code == REG && GP_REG_P (REGNO (dest)) && src_code == CONST_POLY_INT) + { + /* we only want a single full vector register vlen + read after reload. */ + gcc_assert (known_eq (rtx_to_poly_int64 (src), BYTES_PER_RISCV_VECTOR)); + return "csrr\t%0,vlenb"; + } gcc_unreachable (); } diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 63bb3c8debc..2bfab198370 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -148,7 +148,7 @@ ;; scheduling type to be "multi" instead. (define_attr "move_type" "unknown,load,fpload,store,fpstore,mtc,mfc,move,fmove, - const,logical,arith,andi,shift_shift" + const,logical,arith,andi,shift_shift,rdvlenb" (const_string "unknown")) ;; Main data type used by the insn @@ -166,6 +166,35 @@ (const_string "yes")] (const_string "no"))) +;; ISA attributes. +(define_attr "ext" "base,f,d,vector" + (const_string "base")) + +;; True if the extension is enabled. +(define_attr "ext_enabled" "no,yes" + (cond [(eq_attr "ext" "base") + (const_string "yes") + + (and (eq_attr "ext" "f") + (match_test "TARGET_HARD_FLOAT")) + (const_string "yes") + + (and (eq_attr "ext" "d") + (match_test "TARGET_DOUBLE_FLOAT")) + (const_string "yes") + + (and (eq_attr "ext" "vector") + (match_test "TARGET_VECTOR")) + (const_string "yes") + ] + (const_string "no"))) + +;; Attribute to control enable or disable instructions. +(define_attr "enabled" "no,yes" + (cond [(eq_attr "ext_enabled" "no") + (const_string "no")] + (const_string "yes"))) + ;; Classification of each insn. ;; branch conditional branch ;; jump unconditional jump @@ -326,7 +355,8 @@ (eq_attr "dword_mode" "yes")) (const_string "multi") (eq_attr "move_type" "move") (const_string "move") - (eq_attr "move_type" "const") (const_string "const")] + (eq_attr "move_type" "const") (const_string "const") + (eq_attr "move_type" "rdvlenb") (const_string "rdvlenb")] (const_string "unknown"))) ;; Length of instruction in bytes. @@ -1633,24 +1663,26 @@ }) (define_insn "*movdi_32bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m") - (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r,m, *f,*f,*r,*f,*m,r") + (match_operand:DI 1 "move_operand" " r,i,m,r,*J*r,*m,*f,*f,*f,vp"))] "!TARGET_64BIT && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return riscv_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore") - (set_attr "mode" "DI")]) + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") + (set_attr "mode" "DI") + (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) (define_insn "*movdi_64bit" - [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m") - (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f"))] + [(set (match_operand:DI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*f,*m,r") + (match_operand:DI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,*f,vp"))] "TARGET_64BIT && (register_operand (operands[0], DImode) || reg_or_0_operand (operands[1], DImode))" { return riscv_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore") - (set_attr "mode" "DI")]) + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fmove,fpstore,rdvlenb") + (set_attr "mode" "DI") + (set_attr "ext" "base,base,base,base,d,d,d,d,d,vector")]) ;; 32-bit Integer moves @@ -1664,13 +1696,14 @@ }) (define_insn "*movsi_internal" - [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m") - (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f"))] + [(set (match_operand:SI 0 "nonimmediate_operand" "=r,r,r, m, *f,*f,*r,*m,r") + (match_operand:SI 1 "move_operand" " r,T,m,rJ,*r*J,*m,*f,*f,vp"))] "(register_operand (operands[0], SImode) || reg_or_0_operand (operands[1], SImode))" { return riscv_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore") - (set_attr "mode" "SI")]) + [(set_attr "move_type" "move,const,load,store,mtc,fpload,mfc,fpstore,rdvlenb") + (set_attr "mode" "SI") + (set_attr "ext" "base,base,base,base,f,f,f,f,vector")]) ;; 16-bit Integer moves @@ -1689,13 +1722,14 @@ }) (define_insn "*movhi_internal" - [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r") - (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f"))] + [(set (match_operand:HI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") + (match_operand:HI 1 "move_operand" " r,T,m,rJ,*r*J,*f,vp"))] "(register_operand (operands[0], HImode) || reg_or_0_operand (operands[1], HImode))" { return riscv_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtc,mfc") - (set_attr "mode" "HI")]) + [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") + (set_attr "mode" "HI") + (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; HImode constant generation; see riscv_move_integer for details. ;; si+si->hi without truncation is legal because of @@ -1731,13 +1765,14 @@ }) (define_insn "*movqi_internal" - [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r") - (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f"))] + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,r,r, m, *f,*r,r") + (match_operand:QI 1 "move_operand" " r,I,m,rJ,*r*J,*f,vp"))] "(register_operand (operands[0], QImode) || reg_or_0_operand (operands[1], QImode))" { return riscv_output_move (operands[0], operands[1]); } - [(set_attr "move_type" "move,const,load,store,mtc,mfc") - (set_attr "mode" "QI")]) + [(set_attr "move_type" "move,const,load,store,mtc,mfc,rdvlenb") + (set_attr "mode" "QI") + (set_attr "ext" "base,base,base,base,f,f,vector")]) ;; 32-bit floating point moves