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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id s11-20020aa7d78b000000b0042bca34bd15sm9067640edq.95.2022.06.15.04.47.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 15 Jun 2022 04:47:32 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH v2 2/2] riscv-cores.def: Add T-Head XuanTie C906 Date: Wed, 15 Jun 2022 13:47:29 +0200 Message-Id: <20220615114729.826142-2-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220615114729.826142-1-christoph.muellner@vrull.eu> References: <20220615114729.826142-1-christoph.muellner@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-12.3 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_NUMSUBJECT, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner This adds T-Head's XuanTie C906 to the list of known cores as "thead-c906". The C906 is shipped for quite some time (it is the core of the Allwinner D1). Note, that the tuning struct for the C906 is already part of GCC (it is also name "thead-c906"). gcc/ChangeLog: * config/riscv/riscv-cores.def (RISCV_CORE): Add "thead-c906". gcc/testsuite/ChangeLog: * gcc.target/riscv/mcpu-thead-c906.c: New test. Changes since v1: * Adding test case * Reword commit message Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 2 ++ .../gcc.target/riscv/mcpu-thead-c906.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index 60bcadbb034..dd97ece376f 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -44,4 +44,6 @@ RISCV_CORE("sifive-s76", "rv64imafdc", "sifive-7-series") RISCV_CORE("sifive-u54", "rv64imafdc", "sifive-5-series") RISCV_CORE("sifive-u74", "rv64imafdc", "sifive-7-series") +RISCV_CORE("thead-c906", "rv64imafdc", "thead-c906") + #undef RISCV_CORE diff --git a/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c new file mode 100644 index 00000000000..f579e7e2215 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/mcpu-thead-c906.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-skip-if "-march given" { *-*-* } { "-march=*" } } */ +/* { dg-options "-mcpu=thead-c906" { target { rv64 } } } */ +/* T-Head XuanTie C906 => rv64imafdc */ + +#if !((__riscv_xlen == 64) \ + && !defined(__riscv_32e) \ + && defined(__riscv_mul) \ + && defined(__riscv_atomic) \ + && (__riscv_flen == 64) \ + && defined(__riscv_compressed)) +#error "unexpected arch" +#endif + +int main() +{ + return 0; +}