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[62.178.148.172]) by smtp.gmail.com with ESMTPSA id v7-20020a1709062f0700b006fea2705d18sm3805416eji.210.2022.06.13.06.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 13 Jun 2022 06:20:45 -0700 (PDT) From: Christoph Muellner To: gcc-patches@gcc.gnu.org, Kito Cheng , Jim Wilson , Andrew Waterman , Philipp Tomsich , Christoph Muellner Subject: [PATCH 1/2] riscv-cores.def: Fix description of RISCV_CORE() macro Date: Mon, 13 Jun 2022 15:20:41 +0200 Message-Id: <20220613132042.2972081-1-christoph.muellner@vrull.eu> X-Mailer: git-send-email 2.35.3 MIME-Version: 1.0 X-Spam-Status: No, score=-12.0 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Christoph Müllner The current description of RISCV_CORE() does not match the implementation. This commit provides a fix for that. gcc/ChangeLog: * config/riscv/riscv-cores.def: Fix comment. Signed-off-by: Christoph Müllner --- gcc/config/riscv/riscv-cores.def | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def index ecb5e213d98..60bcadbb034 100644 --- a/gcc/config/riscv/riscv-cores.def +++ b/gcc/config/riscv/riscv-cores.def @@ -21,15 +21,13 @@ Before using #include to read this file, define a macro: - RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO) + RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO) The CORE_NAME is the name of the core, represented as a string. - The ARCH is the default arch of the core, represented as a string, - can be NULL if no default arch. - The MICRO_ARCH is the name of the core for which scheduling decisions - will be made, represented as an identifier. - The TUNE_INFO is the detail cost model for this core, represented as an - identifier, reference to riscv-tunes.def. */ + The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i" + or "rv64gc_zifencei"). + The TUNE_INFO is a string that references the detail tuning information + for this core (refer to riscv_tune_info_table for possible values). */ RISCV_CORE("sifive-e20", "rv32imc", "rocket") RISCV_CORE("sifive-e21", "rv32imac", "rocket")