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[1/2] riscv-cores.def: Fix description of RISCV_CORE() macro

Message ID 20220613132042.2972081-1-christoph.muellner@vrull.eu
State New
Headers
Series [1/2] riscv-cores.def: Fix description of RISCV_CORE() macro |

Commit Message

Christoph Müllner June 13, 2022, 1:20 p.m. UTC 
  From: Christoph Müllner <christoph.muellner@vrull.eu>

The current description of RISCV_CORE() does not match the
implementation. This commit provides a fix for that.

gcc/ChangeLog:

	* config/riscv/riscv-cores.def: Fix comment.

Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
---
 gcc/config/riscv/riscv-cores.def | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv-cores.def b/gcc/config/riscv/riscv-cores.def
index ecb5e213d98..60bcadbb034 100644
--- a/gcc/config/riscv/riscv-cores.def
+++ b/gcc/config/riscv/riscv-cores.def
@@ -21,15 +21,13 @@ 
 
    Before using #include to read this file, define a macro:
 
-      RISCV_CORE(CORE_NAME, ARCH, MICRO_ARCH, TUNE_INFO)
+      RISCV_CORE(CORE_NAME, ARCH, TUNE_INFO)
 
    The CORE_NAME is the name of the core, represented as a string.
-   The ARCH is the default arch of the core, represented as a string,
-   can be NULL if no default arch.
-   The MICRO_ARCH is the name of the core for which scheduling decisions
-   will be made, represented as an identifier.
-   The TUNE_INFO is the detail cost model for this core, represented as an
-   identifier, reference to riscv-tunes.def.  */
+   The ARCH is a string describing the supported RISC-V ISA (e.g. "rv32i"
+   or "rv64gc_zifencei").
+   The TUNE_INFO is a string that references the detail tuning information
+   for this core (refer to riscv_tune_info_table for possible values).  */
 
 RISCV_CORE("sifive-e20",      "rv32imc",    "rocket")
 RISCV_CORE("sifive-e21",      "rv32imac",   "rocket")