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[v3,0/9,RISC-V] Atomics improvements

Message ID 20220527060723.235095-1-cmuellner@gcc.gnu.org
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Christoph Müllner May 27, 2022, 6:07 a.m. UTC 
  This series provides a cleanup of the current atomics implementation
of RISC-V (PR100265: Use proper fences for atomic load/store).

The first patch could be squashed into the following patches,
but I found it easier to understand the chances with it in place.

The series has been tested as follows:
* Building and testing a multilib RV32/64 toolchain
  (bootstrapped with riscv-gnu-toolchain repo)
* Manual review of generated sequences for GCC's atomic builtins API

This series was developed more than a year ago, but got never merged.

v1 can be found here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568684.html

v2 can be found here:
https://gcc.gnu.org/pipermail/gcc-patches/2021-May/569691.html

Jim expressed concerns about patch 9/10 (which was inspired by the
AArch64 implementation), that it won't emit the expected CAS sequence
under register pressure. Therefore, I've dropped the patch from the
series in v3.

Changes for v3:
* Rebase/retest on master
* Drop patch 9/10 ("Provide programmatic implementation of CAS")

Changes for v2:
* Guard LL/SC sequence by compiler barriers ("blockage")
  (suggested by Andrew Waterman)
* Changed commit message for AMOSWAP->STORE change
  (suggested by Andrew Waterman)
* Extracted cbranch4 patch from patchset (suggested by Kito Cheng)
* Introduce predicate riscv_sync_memory_operand (suggested by Jim Wilson)
* Fix small code style issue

Christoph Muellner (9):
  RISC-V: Simplify memory model code [PR 100265]
  RISC-V: Emit proper memory ordering suffixes for AMOs [PR 100265]
  RISC-V: Eliminate %F specifier from riscv_print_operand() [PR 100265]
  RISC-V: Use STORE instead of AMOSWAP for atomic stores [PR 100265]
  RISC-V: Emit fences according to chosen memory model [PR 100265]
  RISC-V: Implement atomic_{load,store} [PR 100265]
  RISC-V: Model INSNs for LR and SC [PR 100266]
  RISC-V: Add s.ext-consuming INSNs for LR and SC [PR 100266]
  RISC-V: Introduce predicate "riscv_sync_memory_operand" [PR 100266]

 gcc/config/riscv/riscv.cc |  61 +++----------
 gcc/config/riscv/sync.md  | 183 ++++++++++++++++++++++++++++++--------
 2 files changed, 159 insertions(+), 85 deletions(-)