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([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id k8-20020a2ea288000000b0024f3d1dae84sm2750660lja.12.2022.05.24.15.52.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 15:52:06 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 2/3] RISC-V: Split "(a & (1UL << bitno)) ? 0 : -1" to bext + addi Date: Wed, 25 May 2022 00:51:55 +0200 Message-Id: <20220524225156.4026293-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> References: <20220524225156.4026293-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich , Christoph Muellner Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" For a straightforward application of bext for the following function long bext64(long a, char bitno) { return (a & (1UL << bitno)) ? 0 : -1; } we generate srl a0,a0,a1 # 7 [c=4 l=4] lshrdi3 andi a0,a0,1 # 8 [c=4 l=4] anddi3/1 addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 due to the following failed match at combine time: (set (reg:DI 82) (zero_extract:DI (reg:DI 83) (const_int 1 [0x1]) (reg:DI 84))) The existing pattern for bext requires the 3rd argument to zero_extract to be a QImode register wrapped in a zero_extension. This adds an additional pattern that allows an Xmode argument. With this change, the testcase compiles to bext a0,a0,a1 # 8 [c=4 l=4] *bextdi addi a0,a0,-1 # 14 [c=4 l=4] adddi3/1 gcc/ChangeLog: * config/riscv/bitmanip.md (*bext): Add an additional pattern that allows the 3rd argument to zero_extract to be an Xmode register operand. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbs-bext.c: Add testcases. * gcc.target/riscv/zbs-bexti.c: Add testcases. Signed-off-by: Philipp Tomsich Co-developed-by: Manolis Tsamis --- gcc/config/riscv/bitmanip.md | 12 +++++++++++ gcc/testsuite/gcc.target/riscv/zbs-bext.c | 23 +++++++++++++++++++--- gcc/testsuite/gcc.target/riscv/zbs-bexti.c | 23 ++++++++++++++++------ 3 files changed, 49 insertions(+), 9 deletions(-) diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md index ea5dea13cfb..5d7c20e9fdc 100644 --- a/gcc/config/riscv/bitmanip.md +++ b/gcc/config/riscv/bitmanip.md @@ -332,6 +332,18 @@ (define_insn "*bext" "bext\t%0,%1,%2" [(set_attr "type" "bitmanip")]) +;; When performing `(a & (1UL << bitno)) ? 0 : -1` the combiner +;; usually has the `bitno` typed as X-mode (i.e. no further +;; zero-extension is performed around the bitno). +(define_insn "*bext" + [(set (match_operand:X 0 "register_operand" "=r") + (zero_extract:X (match_operand:X 1 "register_operand" "r") + (const_int 1) + (match_operand:X 2 "register_operand" "r")))] + "TARGET_ZBS" + "bext\t%0,%1,%2" + [(set_attr "type" "bitmanip")]) + (define_insn "*bexti" [(set (match_operand:X 0 "register_operand" "=r") (zero_extract:X (match_operand:X 1 "register_operand" "r") diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bext.c b/gcc/testsuite/gcc.target/riscv/zbs-bext.c index 47982396119..8de9c5a167c 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bext.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bext.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ -/* { dg-skip-if "" { *-*-* } { "-O0" } } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bext */ long @@ -16,6 +16,23 @@ foo1 (long i) return 1L & (i >> 20); } +long bext64_1(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 1 : 0; +} + +long bext64_2(long a, char bitno) +{ + return (a & (1UL << bitno)) ? 0 : -1; +} + +long bext64_3(long a, char bitno) +{ + return (a & (1UL << bitno)) ? -1 : 0; +} + /* { dg-final { scan-assembler-times "bexti\t" 1 } } */ -/* { dg-final { scan-assembler-times "bext\t" 1 } } */ -/* { dg-final { scan-assembler-not "andi" } } */ +/* { dg-final { scan-assembler-times "bext\t" 4 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */ +/* { dg-final { scan-assembler-not "andi" } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c index 99e3b58309c..8182a61707d 100644 --- a/gcc/testsuite/gcc.target/riscv/zbs-bexti.c +++ b/gcc/testsuite/gcc.target/riscv/zbs-bexti.c @@ -1,14 +1,25 @@ /* { dg-do compile } */ -/* { dg-options "-march=rv64gc_zbs -mabi=lp64 -O2" } */ +/* { dg-options "-march=rv64gc_zbs -mabi=lp64" } */ +/* { dg-skip-if "" { *-*-* } { "-O0" "-Og" } } */ /* bexti */ #define BIT_NO 4 -long -foo0 (long a) +long bexti64_1(long a, char bitno) { - return (a & (1 << BIT_NO)) ? 0 : -1; + return (a & (1UL << BIT_NO)) ? 1 : 0; } -/* { dg-final { scan-assembler "bexti" } } */ -/* { dg-final { scan-assembler "addi" } } */ +long bexti64_2(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? 0 : -1; +} + +long bexti64_3(long a, char bitno) +{ + return (a & (1UL << BIT_NO)) ? -1 : 0; +} + +/* { dg-final { scan-assembler-times "bexti\t" 3 } } */ +/* { dg-final { scan-assembler-times "addi\t" 1 } } */ +/* { dg-final { scan-assembler-times "neg\t" 1 } } */ \ No newline at end of file