From patchwork Tue May 24 21:47:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Tomsich X-Patchwork-Id: 54357 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2AF59384402D for ; Tue, 24 May 2022 21:47:56 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-lj1-x236.google.com (mail-lj1-x236.google.com [IPv6:2a00:1450:4864:20::236]) by sourceware.org (Postfix) with ESMTPS id 30A1D3857BAC for ; Tue, 24 May 2022 21:47:13 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 30A1D3857BAC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=vrull.eu Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=vrull.eu Received: by mail-lj1-x236.google.com with SMTP id u7so21717989ljd.11 for ; Tue, 24 May 2022 14:47:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=vrull.eu; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HpryVCj3GWxFgJnjpm5GAK3+bcuviAoOAFvkJwQfiTc=; b=EmKsgcrSqZ1k/Bvh7sS9twHLWhOdVW+QrrRBt+0grreJfTS3UHPBOlAhrwoHXhGZbs xDfBP0bo1H9PwgWj/Niddb8+1cuFpPW0Qndun4y3X5NXb0z75nWB87Y8nx9meOcSQWGQ Pjp2h9klF+VoxfWzUnemFFrh60xAByazes2kvfD88N+/H1DqmCU2SuKIUOGVsFVRXjFF 5VN93xYCND++Kknzc/eLVIQwasKzW3MACtHEcBRVyfH2fsae/dOzhSuXHkIuI1YQ08Ko 6cX3BqCIbZt1PbL+QFAYBUE9yA5AQgNbkvuWwJ0GqkFUvTfef5pi0XH/F+wu/R19xAe7 rTPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HpryVCj3GWxFgJnjpm5GAK3+bcuviAoOAFvkJwQfiTc=; b=hch8L98//geQKJfYbJ39Q9OMlDjUbg6JeySrhq6uIZu8J5VjHKR3o1tfAXscEaH7/P g4oP4m6naUy/lhqEHaBI3KWL/4/A2JjiTtUVE/ySDTiygrZpbgPoWvPu/LI2hE/kQNKg tgEOsB7zrypw1O5b6XXGO7kv7JWh/IfugF1iKTDco1E4tUhkK+DPAqpmQPmuuPN10mfP VEXwkrQhLQbW4ue8yeG8YTNsOVQcFVIUB5Gv9LF8it3GkL94/KDhOtM8GbhDsXQR3M6A 6WnzmDXHjAbXQHmjGzbWp5mSIREggrbXUDiqiNd4/XPfLC95Bkq5qmqHJgNZ2lwq6mUj idxA== X-Gm-Message-State: AOAM530dXtfdhgIpKjvzhfvBb88pRPMhv9uv+5PlyH5/dCQYhSswbz8d Mp/naGOzc7kLIrtAY0RB2exBHdm4AEP+WYgs X-Google-Smtp-Source: ABdhPJxnX6XlLsSvvKdM9XAB+taxpct6eUpRPbTqzkpMgmaTL/8X2xgnmiMKYspx+FGozdvCb47Z1g== X-Received: by 2002:a2e:9d93:0:b0:253:c9bd:288 with SMTP id c19-20020a2e9d93000000b00253c9bd0288mr17118420ljj.223.1653428831455; Tue, 24 May 2022 14:47:11 -0700 (PDT) Received: from ubuntu-focal.. ([2a01:4f9:3a:1e26::2]) by smtp.gmail.com with ESMTPSA id c17-20020a2e9d91000000b0024f3d1dae98sm2724165ljj.32.2022.05.24.14.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 24 May 2022 14:47:10 -0700 (PDT) From: Philipp Tomsich To: gcc-patches@gcc.gnu.org Subject: [PATCH v1 1/3] RISC-V: add consecutive_bits_operand predicate Date: Tue, 24 May 2022 23:47:01 +0200 Message-Id: <20220524214703.4022737-2-philipp.tomsich@vrull.eu> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> References: <20220524214703.4022737-1-philipp.tomsich@vrull.eu> MIME-Version: 1.0 X-Spam-Status: No, score=-11.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, JMQ_SPF_NEUTRAL, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Waterman , Vineet Gupta , Kito Cheng , Philipp Tomsich Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Provide an easy way to constrain for constants that are a a single, consecutive run of ones. gcc/ChangeLog: * config/riscv/predicates.md (consecutive_bits_operand): Implement new predicate. Signed-off-by: Philipp Tomsich --- gcc/config/riscv/predicates.md | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index c37caa2502b..90db5dfcdd5 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -243,3 +243,14 @@ (define_predicate "const63_operand" (define_predicate "imm5_operand" (and (match_code "const_int") (match_test "INTVAL (op) < 5"))) + +;; A CONST_INT operand that consists of a single run of consecutive set bits. +(define_predicate "consecutive_bits_operand" + (match_code "const_int") +{ + unsigned HOST_WIDE_INT val = UINTVAL (op); + if (exact_log2 ((val >> ctz_hwi (val)) + 1) < 0) + return false; + + return true; +})