From patchwork Tue May 24 09:40:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Biener X-Patchwork-Id: 54336 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 5544D385626D for ; Tue, 24 May 2022 09:44:20 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5544D385626D DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653385460; bh=ulPMu83UrcyMoTnm1MVUOT8sSwj/ePa0sR3SqWQVaR8=; h=Date:To:Subject:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=NPs7Ld9FGjUdXv+VD7BMldVXmRW45R1nSuMqBuWAlYYBYyBLZB7u2A1vmHtzDgb/W 55Z72eGol5j3oDFdm31TLZkIarZDmGtXBaxlf7+UeXPAxnzD6KpAP952qnttT7KmJs vSQ1uiwOU/VMS7kAcg5W+Eo0D+PsWsvQHFAZDmuU= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from smtp-out1.suse.de (smtp-out1.suse.de [195.135.220.28]) by sourceware.org (Postfix) with ESMTPS id 73BE33856265 for ; Tue, 24 May 2022 09:40:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 73BE33856265 Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by smtp-out1.suse.de (Postfix) with ESMTPS id 738C9219C4; Tue, 24 May 2022 09:40:24 +0000 (UTC) Received: from imap2.suse-dmz.suse.de (imap2.suse-dmz.suse.de [192.168.254.74]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (P-521) server-digest SHA512) (No client certificate requested) by imap2.suse-dmz.suse.de (Postfix) with ESMTPS id 5BD5E13ADF; Tue, 24 May 2022 09:40:24 +0000 (UTC) Received: from dovecot-director2.suse.de ([192.168.254.65]) by imap2.suse-dmz.suse.de with ESMTPSA id M946FQiojGJECgAAMHmgww (envelope-from ); Tue, 24 May 2022 09:40:24 +0000 Date: Tue, 24 May 2022 11:40:23 +0200 (CEST) To: gcc-patches@gcc.gnu.org Subject: [PATCH] middle-end/105711 - properly handle CONST_INT when expanding bitfields MIME-Version: 1.0 Message-Id: <20220524094024.5BD5E13ADF@imap2.suse-dmz.suse.de> X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Richard Biener via Gcc-patches From: Richard Biener Reply-To: Richard Biener Cc: richard.sandiford@arm.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" This is another place where we fail to pass down the mode of a CONST_INT. Bootstrapped and tested on x86_64-unknown-linux-gnu, OK? Thanks, Richard. 2022-05-24 Richard Biener PR middle-end/105711 * expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter and use it. (extract_bit_field_1): Pass down the mode of op0 to extract_bit_field_as_subreg. * gcc.target/i386/pr105711.c: New testcase. --- gcc/expmed.cc | 15 +++++++++------ gcc/testsuite/gcc.target/i386/pr105711.c | 12 ++++++++++++ 2 files changed, 21 insertions(+), 6 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr105711.c diff --git a/gcc/expmed.cc b/gcc/expmed.cc index 41738c1efe9..e22278370fd 100644 --- a/gcc/expmed.cc +++ b/gcc/expmed.cc @@ -1611,14 +1611,15 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0, static rtx extract_bit_field_as_subreg (machine_mode mode, rtx op0, + machine_mode op0_mode, poly_uint64 bitsize, poly_uint64 bitnum) { poly_uint64 bytenum; if (multiple_p (bitnum, BITS_PER_UNIT, &bytenum) && known_eq (bitsize, GET_MODE_BITSIZE (mode)) - && lowpart_bit_field_p (bitnum, bitsize, GET_MODE (op0)) - && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (op0))) - return simplify_gen_subreg (mode, op0, GET_MODE (op0), bytenum); + && lowpart_bit_field_p (bitnum, bitsize, op0_mode) + && TRULY_NOOP_TRUNCATION_MODES_P (mode, op0_mode)) + return simplify_gen_subreg (mode, op0, op0_mode, bytenum); return NULL_RTX; } @@ -1777,7 +1778,8 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, for valid bitsize and bitnum, so we don't need to do that here. */ if (VECTOR_MODE_P (mode)) { - rtx sub = extract_bit_field_as_subreg (mode, op0, bitsize, bitnum); + rtx sub = extract_bit_field_as_subreg (mode, op0, outermode, + bitsize, bitnum); if (sub) return sub; } @@ -1824,9 +1826,10 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum, /* Extraction of a full MODE1 value can be done with a subreg as long as the least significant bit of the value is the least significant bit of either OP0 or a word of OP0. */ - if (!MEM_P (op0) && !reverse) + if (!MEM_P (op0) && !reverse && op0_mode.exists (&imode)) { - rtx sub = extract_bit_field_as_subreg (mode1, op0, bitsize, bitnum); + rtx sub = extract_bit_field_as_subreg (mode1, op0, imode, + bitsize, bitnum); if (sub) return convert_extracted_bit_field (sub, mode, tmode, unsignedp); } diff --git a/gcc/testsuite/gcc.target/i386/pr105711.c b/gcc/testsuite/gcc.target/i386/pr105711.c new file mode 100644 index 00000000000..6d07e08138a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr105711.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 --param=sccvn-max-alias-queries-per-access=0" } */ + +int *p, a, b; + +void +foo (_Complex char c) +{ + c /= 3040; + a %= __builtin_memcmp (1 + &c, p, 1); + b = c + __imag__ c; +}