middle-end/105711 - properly handle CONST_INT when expanding bitfields

  This is another place where we fail to pass down the mode of a
CONST_INT.

Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?

Thanks,
Richard.

2022-05-24  Richard Biener  <rguenther@suse.de>

	PR middle-end/105711
	* expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter
	and use it.
	(extract_bit_field_1): Pass down the mode of op0 to
	extract_bit_field_as_subreg.

	* gcc.target/i386/pr105711.c: New testcase.
---
 gcc/expmed.cc                            | 15 +++++++++------
 gcc/testsuite/gcc.target/i386/pr105711.c | 12 ++++++++++++
 2 files changed, 21 insertions(+), 6 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr105711.c
  

Richard Biener <rguenther@suse.de> writes:
> This is another place where we fail to pass down the mode of a
> CONST_INT.
>
> Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?
>
> Thanks,
> Richard.
>
> 2022-05-24  Richard Biener  <rguenther@suse.de>
>
> 	PR middle-end/105711
> 	* expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter
> 	and use it.
> 	(extract_bit_field_1): Pass down the mode of op0 to
> 	extract_bit_field_as_subreg.
>
> 	* gcc.target/i386/pr105711.c: New testcase.

LGTM, but I guess the new parameter should be documented above
extract_bit_field_as_subreg.

Thanks,
Richard

> ---
>  gcc/expmed.cc                            | 15 +++++++++------
>  gcc/testsuite/gcc.target/i386/pr105711.c | 12 ++++++++++++
>  2 files changed, 21 insertions(+), 6 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr105711.c
>
> diff --git a/gcc/expmed.cc b/gcc/expmed.cc
> index 41738c1efe9..e22278370fd 100644
> --- a/gcc/expmed.cc
> +++ b/gcc/expmed.cc
> @@ -1611,14 +1611,15 @@ extract_bit_field_using_extv (const extraction_insn *extv, rtx op0,
>  
>  static rtx
>  extract_bit_field_as_subreg (machine_mode mode, rtx op0,
> +			     machine_mode op0_mode,
>  			     poly_uint64 bitsize, poly_uint64 bitnum)
>  {
>    poly_uint64 bytenum;
>    if (multiple_p (bitnum, BITS_PER_UNIT, &bytenum)
>        && known_eq (bitsize, GET_MODE_BITSIZE (mode))
> -      && lowpart_bit_field_p (bitnum, bitsize, GET_MODE (op0))
> -      && TRULY_NOOP_TRUNCATION_MODES_P (mode, GET_MODE (op0)))
> -    return simplify_gen_subreg (mode, op0, GET_MODE (op0), bytenum);
> +      && lowpart_bit_field_p (bitnum, bitsize, op0_mode)
> +      && TRULY_NOOP_TRUNCATION_MODES_P (mode, op0_mode))
> +    return simplify_gen_subreg (mode, op0, op0_mode, bytenum);
>    return NULL_RTX;
>  }
>  
> @@ -1777,7 +1778,8 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
>  	 for valid bitsize and bitnum, so we don't need to do that here.  */
>        if (VECTOR_MODE_P (mode))
>  	{
> -	  rtx sub = extract_bit_field_as_subreg (mode, op0, bitsize, bitnum);
> +	  rtx sub = extract_bit_field_as_subreg (mode, op0, outermode,
> +						 bitsize, bitnum);
>  	  if (sub)
>  	    return sub;
>  	}
> @@ -1824,9 +1826,10 @@ extract_bit_field_1 (rtx str_rtx, poly_uint64 bitsize, poly_uint64 bitnum,
>    /* Extraction of a full MODE1 value can be done with a subreg as long
>       as the least significant bit of the value is the least significant
>       bit of either OP0 or a word of OP0.  */
> -  if (!MEM_P (op0) && !reverse)
> +  if (!MEM_P (op0) && !reverse && op0_mode.exists (&imode))
>      {
> -      rtx sub = extract_bit_field_as_subreg (mode1, op0, bitsize, bitnum);
> +      rtx sub = extract_bit_field_as_subreg (mode1, op0, imode,
> +					     bitsize, bitnum);
>        if (sub)
>  	return convert_extracted_bit_field (sub, mode, tmode, unsignedp);
>      }
> diff --git a/gcc/testsuite/gcc.target/i386/pr105711.c b/gcc/testsuite/gcc.target/i386/pr105711.c
> new file mode 100644
> index 00000000000..6d07e08138a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr105711.c
> @@ -0,0 +1,12 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2 --param=sccvn-max-alias-queries-per-access=0" } */
> +
> +int *p, a, b;
> +
> +void
> +foo (_Complex char c)
> +{
> +  c /= 3040;
> +  a %= __builtin_memcmp (1 + &c, p, 1);
> +  b = c + __imag__ c;
> +}
  

On Tue, 24 May 2022, Richard Sandiford wrote:

> Richard Biener <rguenther@suse.de> writes:
> > This is another place where we fail to pass down the mode of a
> > CONST_INT.
> >
> > Bootstrapped and tested on x86_64-unknown-linux-gnu, OK?
> >
> > Thanks,
> > Richard.
> >
> > 2022-05-24  Richard Biener  <rguenther@suse.de>
> >
> > 	PR middle-end/105711
> > 	* expmed.cc (extract_bit_field_as_subreg): Add op0_mode parameter
> > 	and use it.
> > 	(extract_bit_field_1): Pass down the mode of op0 to
> > 	extract_bit_field_as_subreg.
> >
> > 	* gcc.target/i386/pr105711.c: New testcase.
> 
> LGTM, but I guess the new parameter should be documented above
> extract_bit_field_as_subreg.

Ah, yes - fixed and pushed.

Thanks,
Richard.