diff mbox series

[v3,3/3] RISC-V: Limit regs use for z[f/d]inx extension.

Message ID 20220523100423.2207532-4-jiawei@iscas.ac.cn
State Deferred, archived
Headers
Series RISC-V: Support z[f/d]inx extension |

Commit Message

Jiawei May 23, 2022, 10:04 a.m. UTC 
  From: Jia-Wei Chen <jiawei@iscas.ac.cn>

Limit zfinx abi support with 'ilp32','ilp32e','lp64' only.

Use GPR instead FPR when 'zfinx' enable, Only use even registers in RV32 when 'zdinx' enable.

gcc/ChangeLog:

        * config/riscv/constraints.md (TARGET_HARD_FLOAT ? FP_REGS :
         ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)):
          Use gpr when zfinx or zdinx enable.
        * config/riscv/riscv.c (riscv_hard_regno_mode_ok): Add TARGET_ZFINX.
        (riscv_option_override): Ditto.
        (riscv_abi): Add ABI limit for zfinx with ilp32/lp64.

Co-Authored-By: Sinan Lin.
---
 gcc/config/riscv/constraints.md |  4 ++--
 gcc/config/riscv/riscv.cc       | 14 +++++++++++++-
 2 files changed, 15 insertions(+), 3 deletions(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/constraints.md b/gcc/config/riscv/constraints.md
index bafa4188ccb..0b3d55fee19 100644
--- a/gcc/config/riscv/constraints.md
+++ b/gcc/config/riscv/constraints.md
@@ -21,8 +21,8 @@ 
 
 ;; Register constraints
 
-(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : NO_REGS"
-  "A floating-point register (if available).")
+(define_register_constraint "f" "TARGET_HARD_FLOAT ? FP_REGS : ((TARGET_ZFINX || TARGET_ZDINX) ? GR_REGS : NO_REGS)"
+  "A floating-point register (if available, reuse GPR as FPR when use zfinx).")
 
 (define_register_constraint "j" "SIBCALL_REGS"
   "@internal")
diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc
index ee756aab694..01deef54480 100644
--- a/gcc/config/riscv/riscv.cc
+++ b/gcc/config/riscv/riscv.cc
@@ -4789,6 +4789,13 @@  riscv_hard_regno_mode_ok (unsigned int regno, machine_mode mode)
 	!= call_used_or_fixed_reg_p (regno + i))
       return false;
 
+  /* Only use even registers in RV32 ZDINX */
+  if (!TARGET_64BIT && TARGET_ZDINX){
+    if (GET_MODE_CLASS (mode) == MODE_FLOAT &&
+     GET_MODE_UNIT_SIZE (mode) == GET_MODE_SIZE (DFmode))
+    return !(regno & 1);
+  }
+
   return true;
 }
 
@@ -4980,7 +4987,7 @@  riscv_option_override (void)
     error ("%<-mdiv%> requires %<-march%> to subsume the %<M%> extension");
 
   /* Likewise floating-point division and square root.  */
-  if (TARGET_HARD_FLOAT && (target_flags_explicit & MASK_FDIV) == 0)
+  if ((TARGET_HARD_FLOAT || TARGET_ZFINX) && (target_flags_explicit & MASK_FDIV) == 0)
     target_flags |= MASK_FDIV;
 
   /* Handle -mtune, use -mcpu if -mtune is not given, and use default -mtune
@@ -5026,6 +5033,11 @@  riscv_option_override (void)
   if (TARGET_RVE && riscv_abi != ABI_ILP32E)
     error ("rv32e requires ilp32e ABI");
 
+  // Zfinx require abi ilp32,ilp32e or lp64.
+  if (TARGET_ZFINX && riscv_abi != ABI_ILP32
+      && riscv_abi != ABI_LP64 && riscv_abi != ABI_ILP32E)
+    error ("z*inx requires ABI ilp32, ilp32e or lp64");
+
   /* We do not yet support ILP32 on RV64.  */
   if (BITS_PER_WORD != POINTER_SIZE)
     error ("ABI requires %<-march=rv%d%>", POINTER_SIZE);