From patchwork Mon May 23 10:04:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 54278 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 2E9FE383A32C for ; Mon, 23 May 2022 10:04:57 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp84.cstnet.cn [159.226.251.84]) by sourceware.org (Postfix) with ESMTP id A1756383E6BC for ; Mon, 23 May 2022 10:04:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A1756383E6BC Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.112.183.207]) by APP-05 (Coremail) with SMTP id zQCowADXXhs0XIti6Yr9CQ--.27163S3; Mon, 23 May 2022 18:04:37 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v3 1/3] RISC-V: Minimal support of z[f/d]inx extension. Date: Mon, 23 May 2022 18:04:21 +0800 Message-Id: <20220523100423.2207532-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220523100423.2207532-1-jiawei@iscas.ac.cn> References: <20220523100423.2207532-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADXXhs0XIti6Yr9CQ--.27163S3 X-Coremail-Antispam: 1UD129KBjvJXoWxuFy8XFWUtry8JrykXF1DJrb_yoWrJF43pa 1rW34Yy34Fqan3Wa17try8W3yUJ3Z5KryrJa1ku347Aa1DJrWDAFn8uw1S9r4kXFZ0vrn2 y3WY9w1Yva1UGa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUB214x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Xr0_Ar1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwCY02Avz4vE174l42xK82IYc2 Ij64vIr41l4I8I3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s02 6x8GjcxK67AKxVWUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0x vE2Ix0cI8IcVAFwI0_Jr0_JF4lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4j6F4UMIIF0xvE 42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6x kF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjfUUGYpUUUUU X-Originating-IP: [47.112.183.207] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiBgkPAF0TgPUp7QAAs- X-Spam-Status: No, score=-11.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariqandlaura@gmail.com, Jia-Wei Chen , wuwei2016@iscas.ac.cn, kito.cheng@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Jia-Wei Chen Minimal support of zfinx extension, include 'zfinx' and 'zdinx' corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f'. gcc/ChangeLog: * common/config/riscv/riscv-common.cc: Add z[f/d]inx extension info. * config/riscv/arch-canonicalize: Add imply info. * config/riscv/riscv-opts.h (MASK_ZFINX): New. (MASK_ZDINX): Ditto. (TARGET_ZFINX): Ditto. (TARGET_ZDINX): Ditto. * config/riscv/riscv.opt: New. Co-Authored-By: Sinan Lin --- gcc/common/config/riscv/riscv-common.cc | 9 +++++++++ gcc/config/riscv/arch-canonicalize | 3 +++ gcc/config/riscv/riscv-opts.h | 6 ++++++ gcc/config/riscv/riscv.opt | 3 +++ 4 files changed, 21 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index 1501242e296..124bccb23ce 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -50,6 +50,9 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + {"zdinx", "zfinx"}, + {"zfinx", "zicsr"}, + {"zk", "zkn"}, {"zk", "zkr"}, {"zk", "zkt"}, @@ -154,6 +157,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1099,6 +1105,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX}, + {"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB}, {"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC}, {"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX}, diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index 41bab69193c..e4cfae40b8a 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -41,6 +41,9 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] IMPLIED_EXT = { "d" : ["f", "zicsr"], "f" : ["zicsr"], + "zdinx" : ["zfinx", "zicsr"], + "zfinx" : ["zicsr"], + "zk" : ["zkn", "zkr", "zkt"], "zkn" : ["zbkb", "zbkc", "zbkx", "zkne", "zknd", "zknh"], "zks" : ["zbkb", "zbkc", "zbkx", "zksed", "zksh"], diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 15bb5e76854..4faf62616d3 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,6 +83,12 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 0) + +#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0) + #define MASK_ZBKB (1 << 0) #define MASK_ZBKC (1 << 1) #define MASK_ZBKX (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 84c8cf5a2de..18fd11e3a51 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -200,6 +200,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zf_subext + TargetVariable int riscv_zk_subext