From patchwork Fri May 20 04:59:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 54252 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 629F5383542B for ; Fri, 20 May 2022 05:00:32 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 629F5383542B DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1653022832; bh=ehJWVjxvvHQKWFMbd7xU3QcUaS8dvZQdIOxC8ZHa/pQ=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=mwaRzytLXJcdrkguj37LdMDKcuTsp8EgUS7f2eeovrExSd6flRjTTtCguHCb7xDNj OBCYRARZhw14YZZDkZgdKXPSrFG2lB9YlBU/raSsAvq+hsidRjajlP/uHrHQH9Crd7 PswWpDEssZ0pGynMKdyFIi/Cm05qLtdV1oAXWiKI= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 85FB13835813 for ; Fri, 20 May 2022 05:00:01 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 85FB13835813 X-IronPort-AV: E=McAfee;i="6400,9594,10352"; a="272192398" X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="272192398" Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 May 2022 22:00:00 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,238,1647327600"; d="scan'208";a="899140739" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga005.fm.intel.com with ESMTP; 19 May 2022 21:59:59 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 24K4xwJP007268; Thu, 19 May 2022 21:59:59 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] Increase move cost between mask and gpr. Date: Fri, 20 May 2022 12:59:58 +0800 Message-Id: <20220520045958.70516-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" kmovd only uses port5 which is often the bottleneck of performance. Also from latency perspective, spill and reload mostly could be STLF or even MRN which only take 1 cycle. So the patch increase move cost between gpr and mask to be the same as gpr <-> sse register. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready to push to trunk. gcc/ChangeLog: * config/i386/x86-tune-costs.h (skylake_cost): Increase gpr <-> mask cost from 5 to 6. (icelake_cost): Ditto. gcc/testsuite/ChangeLog: * gcc.target/i386/spill_to_mask-1.c: New test. --- gcc/config/i386/x86-tune-costs.h | 4 ++-- gcc/testsuite/gcc.target/i386/spill_to_mask-1.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/config/i386/x86-tune-costs.h b/gcc/config/i386/x86-tune-costs.h index 017ffa69958..05cbd49ec87 100644 --- a/gcc/config/i386/x86-tune-costs.h +++ b/gcc/config/i386/x86-tune-costs.h @@ -1866,7 +1866,7 @@ struct processor_costs skylake_cost = { {8, 8, 8, 12, 24}, /* cost of storing SSE registers in 32,64,128,256 and 512-bit */ 6, 6, /* SSE->integer and integer->SSE moves */ - 5, 5, /* mask->integer and integer->mask moves */ + 6, 6, /* mask->integer and integer->mask moves */ {8, 8, 8}, /* cost of loading mask register in QImode, HImode, SImode. */ {6, 6, 6}, /* cost if storing mask register @@ -1992,7 +1992,7 @@ struct processor_costs icelake_cost = { {8, 8, 8, 12, 24}, /* cost of storing SSE registers in 32,64,128,256 and 512-bit */ 6, 6, /* SSE->integer and integer->SSE moves */ - 5, 5, /* mask->integer and integer->mask moves */ + 6, 6, /* mask->integer and integer->mask moves */ {8, 8, 8}, /* cost of loading mask register in QImode, HImode, SImode. */ {6, 6, 6}, /* cost if storing mask register diff --git a/gcc/testsuite/gcc.target/i386/spill_to_mask-1.c b/gcc/testsuite/gcc.target/i386/spill_to_mask-1.c index 94d6764fc56..be19239a685 100644 --- a/gcc/testsuite/gcc.target/i386/spill_to_mask-1.c +++ b/gcc/testsuite/gcc.target/i386/spill_to_mask-1.c @@ -120,7 +120,7 @@ void foo (DTYPE in[16], DTYPE out[8], const DTYPE C[16]) out[7] += h; } -/* { dg-final { scan-assembler "kmovd" } } */ +/* { dg-final { scan-assembler "kmovd" { xfail *-*-* } } } */ /* { dg-final { scan-assembler-not "knot" } } */ /* { dg-final { scan-assembler-not "kxor" } } */ /* { dg-final { scan-assembler-not "kor" } } */