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Tue, 10 May 2022 11:25:54 +0800 (CST) From: shiyulong@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH V4 3/3] RISC-V:Cache Management Operation instructions testcases Date: Tue, 10 May 2022 11:25:26 +0800 Message-Id: <20220510032526.11560-4-shiyulong@iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220510032526.11560-1-shiyulong@iscas.ac.cn> References: <20220510032526.11560-1-shiyulong@iscas.ac.cn> X-CM-TRANSID: qwCowAAHnhU323lioBtBBQ--.37585S5 X-Coremail-Antispam: 1UD129KBjvJXoWxKF4rGw4fAF47WFyrXw4fXwb_yoW7ZFy3p3 97Gw4IvrWrZF97Grs3GF1UJwsIvrs2gry5u3s7CryUXrs7trW2q3Z7trW7Jr45JF1UJryf ua129a1ru3Wjqw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr1j6F4UJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Cr1j6rxd M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4kE6xkIj40Ew7xC0wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUPHUDUUUUU= X-Originating-IP: [47.88.16.30] X-CM-SenderInfo: 5vkl53porqwq5lvft2wodfhubq/ X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: andrew@sifive.com, yulong , kito.cheng@gmail.com, jiawei@iscas.ac.cn, wuwei2016@iscas.ac.cn, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong This commit adds testcases about CMO instructions. gcc/testsuite/ChangeLog: * gcc.target/riscv/cmo-zicbom-1.c: New test. * gcc.target/riscv/cmo-zicbom-2.c: New test. * gcc.target/riscv/cmo-zicbop-1.c: New test. * gcc.target/riscv/cmo-zicbop-2.c: New test. * gcc.target/riscv/cmo-zicboz-1.c: New test. * gcc.target/riscv/cmo-zicboz-2.c: New test. --- gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c | 21 +++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c | 23 +++++++++++++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c | 9 ++++++++ gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c | 9 ++++++++ 6 files changed, 106 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c create mode 100644 gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c new file mode 100644 index 00000000000..e2ba2183511 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-1.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicbom -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_zicbom_cbo_clean(); +} + +int foo2() +{ + return __builtin_riscv_zicbom_cbo_flush(); +} + +int foo3() +{ + return __builtin_riscv_zicbom_cbo_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c new file mode 100644 index 00000000000..a605e8b1bdc --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbom-2.c @@ -0,0 +1,21 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicbom -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_zicbom_cbo_clean(); +} + +int foo2() +{ + return __builtin_riscv_zicbom_cbo_flush(); +} + +int foo3() +{ + return __builtin_riscv_zicbom_cbo_inval(); +} + +/* { dg-final { scan-assembler-times "cbo.clean" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.flush" 1 } } */ +/* { dg-final { scan-assembler-times "cbo.inval" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c new file mode 100644 index 00000000000..c5d78c1763d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-1.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv64-*-*}}} */ +/* { dg-options "-march=rv64gc_zicbop -mabi=lp64" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_zicbop_cbo_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c new file mode 100644 index 00000000000..6576365b39c --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicbop-2.c @@ -0,0 +1,23 @@ +/* { dg-do compile target { { rv32-*-*}}} */ +/* { dg-options "-march=rv32gc_zicbop -mabi=ilp32" } */ + +void foo (char *p) +{ + __builtin_prefetch (p, 0, 0); + __builtin_prefetch (p, 0, 1); + __builtin_prefetch (p, 0, 2); + __builtin_prefetch (p, 0, 3); + __builtin_prefetch (p, 1, 0); + __builtin_prefetch (p, 1, 1); + __builtin_prefetch (p, 1, 2); + __builtin_prefetch (p, 1, 3); +} + +int foo1() +{ + return __builtin_riscv_zicbop_cbo_prefetchi(1); +} + +/* { dg-final { scan-assembler-times "prefetch.i" 1 } } */ +/* { dg-final { scan-assembler-times "prefetch.r" 4 } } */ +/* { dg-final { scan-assembler-times "prefetch.w" 4 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c new file mode 100644 index 00000000000..96c1674ef2d --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-1.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zicboz -mabi=lp64" } */ + +int foo1() +{ + return __builtin_riscv_zicboz_cbo_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */ diff --git a/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c new file mode 100644 index 00000000000..9d99839b1e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/cmo-zicboz-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32gc_zicboz -mabi=ilp32" } */ + +int foo1() +{ + return __builtin_riscv_zicboz_cbo_zero(); +} + +/* { dg-final { scan-assembler-times "cbo.zero" 1 } } */