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Mon, 9 May 2022 14:35:36 +0000 To: Subject: [PATCH 08/10] testsuite: Add C++ unwinding tests with Decimal Floating-Point Date: Mon, 9 May 2022 16:35:05 +0200 Message-ID: <20220509143507.239804-9-christophe.lyon@arm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509143507.239804-1-christophe.lyon@arm.com> References: <20220509143507.239804-1-christophe.lyon@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-Correlation-Id: 978d96af-b7a2-4e62-791f-08da31c93226 X-MS-TrafficTypeDiagnostic: PR2PR08MB4683:EE_|VE1EUR03FT012:EE_|DB9PR08MB6475:EE_ X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: Ksn+8X4DQJfPvuHXAnPUnmfSe38ejuL1SbRWjb4Df7Di+u0i/jYyObeR7xfCLOW99m9rrgXh+w3EcEhdfji9MQ0eOzXYfHmFy6lVo97XmTMIJyYBBPwBTt2TuNMNNAAPybzfl1aDNeGn25/AdTlhANvwmopzTIHF11xx5JzLhIllOiFoAEPH+zkqPebalvSt1t8rT7fQQskj2nsvb6NOFCFeszyxG3YZQkiHTtN9H4IQyU7xgsqGSrp2fuTpsKaTEAViCIoK2UJaIR1vk+FLcrhzelJ6sPhp1EdZBRjdX6CMimtov5hhVqQAUnZ4Mq4f9CZmpoY1t3g5WD7Zbp9XYHDSzVxieRtMrFUfxBTYyIgqfvBYymSH+S5ucMyxgFw85BG3WwlicNkthYjgDsBJfOrNHeAk3Sip45/3+WuxYi61WWjtPo2Yn2mLtosniuvk6Dj6JeexJMZ+Oyfujqxjul0/5EqaIRMtoHF6pRGMRwQHe9UGw5aPWDzZcSb5KyNx+V7ypqUclWKRYa+Ag+/Xe2tO75BUxAuxkcsvwbjbtUJH/vwUcqCqZ+VR8FulQnC2lRHItTKz6kuY/yTWq6J7JCjVMEz4+nsBJXMz8LrI0gYSGbwndivksAvKlDNw7JB/G8Gq4cKtlSN23PnZc9feCfDHuUDb0vIA6qVZ+vX4RiixiCRzPa3H5d499onSn/kXggXvR5B0QD5esFchc9uX9g== X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234; 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+ +#include + +using namespace std::decimal; + +int +foo (double fp) +{ + if (fp < 32.0) + throw (decimal32)32; + if (fp < 64.0) + throw (decimal64)64; + if (fp < 128.0) + throw (decimal128)128; + return 0; +} + +int bar (double fp) +{ + try + { + foo (fp); + abort (); + } + catch (decimal32 df) + { + if (df != (decimal32)32) + abort (); + } + catch (decimal64 dd) + { + if (dd != (decimal64)64) + abort (); + } + catch (decimal128 dl) + { + if (dl != (decimal128)128) + abort (); + } + return 0; +} + +int +main () +{ + bar (10.0); + bar (20.0); + bar (100.0); + return 0; +} diff --git a/gcc/testsuite/g++.dg/eh/dfp-2.C b/gcc/testsuite/g++.dg/eh/dfp-2.C new file mode 100644 index 00000000000..aff0e03d1d9 --- /dev/null +++ b/gcc/testsuite/g++.dg/eh/dfp-2.C @@ -0,0 +1,54 @@ +// { dg-do run } +// { dg-require-effective-target dfp } + +extern "C" void abort (); + +typedef float dec32 __attribute__((mode(SD))); +typedef float dec64 __attribute__((mode(DD))); +typedef float dec128 __attribute__((mode(TD))); + +int +foo (double fp) +{ + if (fp < 32.0) + throw (dec32)32; + if (fp < 64.0) + throw (dec64)64; + if (fp < 128.0) + throw (dec128)128; + return 0; +} + +int bar (double fp) +{ + try + { + foo (fp); + abort (); + } + catch (dec32 df) + { + if (df != (dec32)32) + abort (); + } + catch (dec64 dd) + { + if (dd != (dec64)64) + abort (); + } + catch (dec128 dl) + { + if (dl != (dec128)128) + abort (); + } + return 0; +} + +int +main () +{ + bar (10.0); + bar (20.0); + bar (100.0); + return 0; +} diff --git a/gcc/testsuite/g++.dg/eh/dfp-saves-aarch64.C b/gcc/testsuite/g++.dg/eh/dfp-saves-aarch64.C new file mode 100644 index 00000000000..79f6697dd10 --- /dev/null +++ b/gcc/testsuite/g++.dg/eh/dfp-saves-aarch64.C @@ -0,0 +1,49 @@ +// { dg-do run { target aarch64*-*-* } } +// { dg-require-effective-target dfp } + +/* Test unwinding of AArch64 register saves. */ +/* We cannot use #include because it defines + decimal* types as classes, which we cannot be assigned to register + variables. Hence the use the mode attribute trick. */ + +#ifdef __aarch64__ + +typedef float dec64 __attribute__((mode(DD))); + +extern "C" void abort (void); +extern "C" void exit (int); + +void +foo (void) +{ + register dec64 v10 asm("v10") = 0; + register dec64 v11 asm("v11") = 1; + register dec64 v12 asm("v12") = 2; + register dec64 v13 asm("v13") = 3; + asm volatile ("" : "+w" (v10), "+w" (v11), "+w" (v12), "+w" (v13)); + throw ""; +} + +int +main (void) +{ + register dec64 v10 asm("v10") = 10; + register dec64 v11 asm("v11") = 11; + register dec64 v12 asm("v12") = 12; + register dec64 v13 asm("v13") = 13; + asm volatile ("" : "+w" (v10), "+w" (v11), "+w" (v12), "+w" (v13)); + try { + foo (); + } catch (...) { + asm volatile ("" : "+w" (v10), "+w" (v11), "+w" (v12), "+w" (v13)); + if (v10 != 10 || v11 != 11 || v12 != 12 || v13 != 13) + abort (); + } + exit (0); +} +#else +int +main (void) +{ +} +#endif