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AQAAf9AxCs1QoTVi0hYMAA--.20946S13; Sat, 19 Mar 2022 17:25:04 +0800 (CST) From: chenglulu To: gcc-patches@gcc.gnu.org Subject: [PATCH v9 11/12] LoongArch Port: gcc/testsuite Date: Sat, 19 Mar 2022 17:24:24 +0800 Message-Id: <20220319092425.3324697-12-chenglulu@loongson.cn> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220319092425.3324697-1-chenglulu@loongson.cn> References: <20220319092425.3324697-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9AxCs1QoTVi0hYMAA--.20946S13 X-Coremail-Antispam: 1UD129KBjvAXoWfZr45GF1kXr17trW8Cr1DAwb_yoW8tFW3Zo ZYkFyUJw4fGw13CFWqkr4UuryUW34v9rs8ZFWYyFWrC3WUGw13C3s8Cw1xAr1UKw4fXFWU ZFykKaykJrWDW3s3n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUYu7AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 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X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: richard.sandiford@arm.com, xuchenghua@loongson.cn, chenglulu , joseph@codesourcery.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" gcc/testsuite/ * g++.dg/cpp0x/constexpr-rom.C: Add build options for LoongArch. * g++.old-deja/g++.abi/ptrmem.C: Add LoongArch support. * g++.old-deja/g++.pt/ptrmem6.C: xfail for LoongArch. * gcc.dg/20020312-2.c: Add LoongArch support. * c-c++-common/zero-scratch-regs-10.c: Like wise * c-c++-common/zero-scratch-regs-11.c: Like wise * c-c++-common/zero-scratch-regs-8.c: Like wise * c-c++-common/zero-scratch-regs-9.c: Like wise * gcc.dg/loop-8.c: Skip on LoongArch. * gcc.dg/torture/stackalign/builtin-apply-2.c: Likewise. * gcc.dg/tree-ssa/ssa-fre-3.c: Likewise. * go.test/go-test.exp: Define the LoongArch target. * lib/target-supports.exp: Like wise. * gcc.target/loongarch/loongarch.exp: New file. * gcc.target/loongarch/tst-asm-const.c: Like wise. * gcc.target/loongarch/larch-builtin.c: Like wise. --- .../c-c++-common/zero-scratch-regs-10.c | 2 +- .../c-c++-common/zero-scratch-regs-11.c | 2 +- .../c-c++-common/zero-scratch-regs-8.c | 2 +- .../c-c++-common/zero-scratch-regs-9.c | 2 +- gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C | 2 +- gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C | 2 +- gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C | 2 +- gcc/testsuite/gcc.dg/20020312-2.c | 2 + gcc/testsuite/gcc.dg/loop-8.c | 2 +- .../torture/stackalign/builtin-apply-2.c | 2 +- gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c | 2 +- .../gcc.target/loongarch/larch-builtin.c | 307 ++++++++++++++++++ .../gcc.target/loongarch/loongarch.exp | 40 +++ .../gcc.target/loongarch/tst-asm-const.c | 16 + gcc/testsuite/go.test/go-test.exp | 3 + gcc/testsuite/lib/target-supports.exp | 14 + 16 files changed, 392 insertions(+), 10 deletions(-) create mode 100644 gcc/testsuite/gcc.target/loongarch/larch-builtin.c create mode 100644 gcc/testsuite/gcc.target/loongarch/loongarch.exp create mode 100644 gcc/testsuite/gcc.target/loongarch/tst-asm-const.c diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c index 96e0b79b328..a89de4850a6 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-10.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2" } */ #include diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c index 0714f95a04f..b7739b2c6f6 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-11.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-10.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c index aceda7e5cb8..067b2c67778 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-8.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all-arg" } */ #include "zero-scratch-regs-1.c" diff --git a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c index f3152a7a732..ea83bc146b7 100644 --- a/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c +++ b/gcc/testsuite/c-c++-common/zero-scratch-regs-9.c @@ -1,5 +1,5 @@ /* { dg-do run } */ -/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* } } } */ +/* { dg-skip-if "not implemented" { ! { i?86*-*-* x86_64*-*-* sparc*-*-* aarch64*-*-* arm*-*-* nvptx*-*-* s390*-*-* loongarch64*-*-* } } } */ /* { dg-options "-O2 -fzero-call-used-regs=all" } */ #include "zero-scratch-regs-1.c" diff --git a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C index 2e0ef685f36..424979a604b 100644 --- a/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C +++ b/gcc/testsuite/g++.dg/cpp0x/constexpr-rom.C @@ -1,6 +1,6 @@ // PR c++/49673: check that test_data goes into .rodata // { dg-do compile { target c++11 } } -// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } } +// { dg-additional-options -G0 { target { { alpha*-*-* frv*-*-* ia64-*-* lm32*-*-* m32r*-*-* microblaze*-*-* mips*-*-* loongarch*-*-* nios2-*-* powerpc*-*-* rs6000*-*-* } && { ! { *-*-darwin* *-*-aix* alpha*-*-*vms* } } } } } // { dg-final { scan-assembler "\\.rdata" { target mips*-*-* } } } // { dg-final { scan-assembler "rodata" { target { { *-*-linux-gnu *-*-gnu* *-*-elf } && { ! { mips*-*-* riscv*-*-* } } } } } } diff --git a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C index bda7960d8a2..f69000e9081 100644 --- a/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C +++ b/gcc/testsuite/g++.old-deja/g++.abi/ptrmem.C @@ -7,7 +7,7 @@ function. However, some platforms use all bits to encode a function pointer. Such platforms use the lowest bit of the delta, that is shifted left by one bit. */ -#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ +#if defined __MN10300__ || defined __SH5__ || defined __arm__ || defined __thumb__ || defined __mips__ || defined __aarch64__ || defined __PRU__ || defined __loongarch__ #define ADJUST_PTRFN(func, virt) ((void (*)())(func)) #define ADJUST_DELTA(delta, virt) (((delta) << 1) + !!(virt)) #else diff --git a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C index 9f4bbe43f89..8f8f7017ab7 100644 --- a/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C +++ b/gcc/testsuite/g++.old-deja/g++.pt/ptrmem6.C @@ -25,7 +25,7 @@ int main() { h<&B::j>(); // { dg-error "" } g<(void (A::*)()) &A::f>(); // { dg-error "" "" { xfail c++11 } } h<(int A::*) &A::i>(); // { dg-error "" "" { xfail c++11 } } - g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* } } } } + g<(void (A::*)()) &B::f>(); // { dg-error "" "" { xfail { c++11 && { aarch64*-*-* arm*-*-* mips*-*-* loongarch*-*-* } } } } h<(int A::*) &B::j>(); // { dg-error "" } g<(void (A::*)()) 0>(); // { dg-error "" "" { target { ! c++11 } } } h<(int A::*) 0>(); // { dg-error "" "" { target { ! c++11 } } } diff --git a/gcc/testsuite/gcc.dg/20020312-2.c b/gcc/testsuite/gcc.dg/20020312-2.c index 52c33d09b90..92bc150df0f 100644 --- a/gcc/testsuite/gcc.dg/20020312-2.c +++ b/gcc/testsuite/gcc.dg/20020312-2.c @@ -37,6 +37,8 @@ extern void abort (void); /* PIC register is r1, but is used even without -fpic. */ #elif defined(__lm32__) /* No pic register. */ +#elif defined(__loongarch__) +/* No pic register. */ #elif defined(__M32R__) /* No pic register. */ #elif defined(__m68k__) diff --git a/gcc/testsuite/gcc.dg/loop-8.c b/gcc/testsuite/gcc.dg/loop-8.c index a685fc25056..8e5f2087831 100644 --- a/gcc/testsuite/gcc.dg/loop-8.c +++ b/gcc/testsuite/gcc.dg/loop-8.c @@ -1,6 +1,6 @@ /* { dg-do compile } */ /* { dg-options "-O1 -fdump-rtl-loop2_invariant" } */ -/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-*" } } */ +/* { dg-skip-if "unexpected IV" { "hppa*-*-* mips*-*-* visium-*-* powerpc*-*-* riscv*-*-* mmix-*-* vax-*-* loongarch*-*-*" } } */ /* Load immediate on condition is available from z13 on and prevents moving the load out of the loop, so always run this test with -march=zEC12 that does not have load immediate on condition. */ diff --git a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c index 5ec05587dba..552ca1433f4 100644 --- a/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c +++ b/gcc/testsuite/gcc.dg/torture/stackalign/builtin-apply-2.c @@ -9,7 +9,7 @@ /* arm_hf_eabi: Variadic funcs use Base AAPCS. Normal funcs use VFP variant. avr: Variadic funcs don't pass arguments in registers, while normal funcs do. */ -/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* } } } */ +/* { dg-skip-if "Variadic funcs use different argument passing from normal funcs" { arm_hf_eabi || { csky*-*-* avr-*-* riscv*-*-* or1k*-*-* msp430-*-* amdgcn-*-* pru-*-* loongarch*-*-* } } } */ /* { dg-skip-if "Variadic funcs have all args on stack. Normal funcs have args in registers." { nds32*-*-* } { v850*-*-* } } */ /* { dg-require-effective-target untyped_assembly } */ diff --git a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c index 6b6255b9713..224dd4f72ef 100644 --- a/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c +++ b/gcc/testsuite/gcc.dg/tree-ssa/ssa-fre-3.c @@ -5,7 +5,7 @@ When the condition is true, we distribute "(int) (a + b)" as "(int) a + (int) b", otherwise we keep the original. */ -/* { dg-do compile { target { ! mips64 } } } */ +/* { dg-do compile { target { ! mips64 } && { ! loongarch64 } } } */ /* { dg-options "-O -fno-tree-forwprop -fno-tree-ccp -fwrapv -fdump-tree-fre1-details" } */ /* From PR14844. */ diff --git a/gcc/testsuite/gcc.target/loongarch/larch-builtin.c b/gcc/testsuite/gcc.target/loongarch/larch-builtin.c new file mode 100644 index 00000000000..74d17bf9043 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/larch-builtin.c @@ -0,0 +1,307 @@ +/* Test for LoongArch intrinsics. */ + +/* { dg-do compile } */ + +/* { dg-final { scan-assembler-times "test_rdtime_d:.*rdtime\\.d.*\\.size test_rdtime_d" 1 } } */ +/* { dg-final { scan-assembler-times "test_rdtimeh_w:.*rdtimeh\\.w.*\\.size test_rdtimeh_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_rdtimel_w:.*rdtimel\\.w.*\\.size test_rdtimel_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_movfcsr2gr:.*movfcsr2gr.*\\.size test_movfcsr2gr" 1 } } */ +/* { dg-final { scan-assembler-times "test_movgr2fcsr:.*movgr2fcsr.*\\.size test_movgr2fcsr" 1 } } */ +/* { dg-final { scan-assembler-times "test_dcacop:.*cacop.*\\.size test_dcacop" 1 } } */ +/* { dg-final { scan-assembler-times "test_cpucfg:.*cpucfg.*\\.size test_cpucfg" 1 } } */ +/* { dg-final { scan-assembler-times "test_asrtle_d:.*asrtle\\.d.*\\.size test_asrtle_d" 1 } } */ +/* { dg-final { scan-assembler-times "test_asrtgt_d:.*asrtgt\\.d.*\\.size test_asrtgt_d" 1 } } */ +/* { dg-final { scan-assembler-times "test_dlddir:.*lddir.*\\.size test_dlddir" 1 } } */ +/* { dg-final { scan-assembler-times "test_dldpte:.*ldpte.*\\.size test_dldpte" 1 } } */ +/* { dg-final { scan-assembler-times "test_crc_w_b_w:.*crc\\.w\\.b\\.w.*\\.size test_crc_w_b_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crc_w_h_w:.*crc\\.w\\.h\\.w.*\\.size test_crc_w_h_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crc_w_w_w:.*crc\\.w\\.w\\.w.*\\.size test_crc_w_w_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crc_w_d_w:.*crc\\.w\\.d\\.w.*\\.size test_crc_w_d_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crcc_w_b_w:.*crcc\\.w\\.b\\.w.*\\.size test_crcc_w_b_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crcc_w_h_w:.*crcc\\.w\\.h\\.w.*\\.size test_crcc_w_h_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crcc_w_w_w:.*crcc\\.w\\.w\\.w.*\\.size test_crcc_w_w_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_crcc_w_d_w:.*crcc\\.w\\.d\\.w.*\\.size test_crcc_w_d_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_csrrd:.*csrrd.*\\.size test_csrrd" 1 } } */ +/* { dg-final { scan-assembler-times "test_csrwr:.*csrwr.*\\.size test_csrwr" 1 } } */ +/* { dg-final { scan-assembler-times "test_csrxchg:.*csrxchg.*\\.size test_csrxchg" 1 } } */ +/* { dg-final { scan-assembler-times "test_dcsrrd:.*csrrd.*\\.size test_dcsrrd" 1 } } */ +/* { dg-final { scan-assembler-times "test_dcsrwr:.*csrwr.*\\.size test_dcsrwr" 1 } } */ +/* { dg-final { scan-assembler-times "test_dcsrxchg:.*csrxchg.*\\.size test_dcsrxchg" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrrd_b:.*iocsrrd\\.b.*\\.size test_iocsrrd_b" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrrd_h:.*iocsrrd\\.h.*\\.size test_iocsrrd_h" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrrd_w:.*iocsrrd\\.w.*\\.size test_iocsrrd_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrrd_d:.*iocsrrd\\.d.*\\.size test_iocsrrd_d" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrwr_b:.*iocsrwr\\.b.*\\.size test_iocsrwr_b" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrwr_h:.*iocsrwr\\.h.*\\.size test_iocsrwr_h" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrwr_w:.*iocsrwr\\.w.*\\.size test_iocsrwr_w" 1 } } */ +/* { dg-final { scan-assembler-times "test_iocsrwr_d:.*iocsrwr\\.d.*\\.size test_iocsrwr_d" 1 } } */ +/* { dg-final { scan-assembler-times "test_dbar:.*dbar.*\\.size test_dbar" 1 } } */ +/* { dg-final { scan-assembler-times "test_ibar:.*ibar.*\\.size test_ibar" 1 } } */ +/* { dg-final { scan-assembler-times "test_syscall:.*syscall.*\\.size test_syscall" 1 } } */ +/* { dg-final { scan-assembler-times "test_break:.*break.*\\.size test_break" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbsrch:.*tlbsrch.*\\.size test_tlbsrch" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbrd:.*tlbrd.*\\.size test_tlbrd" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbwr:.*tlbwr.*\\.size test_tlbwr" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbfill:.*tlbfill.*\\.size test_tlbfill" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbclr:.*tlbclr.*\\.size test_tlbclr" 1 } } */ +/* { dg-final { scan-assembler-times "test_tlbflush:.*tlbflush.*\\.size test_tlbflush" 1 } } */ + +#include + +__drdtime_t +test_rdtime_d () +{ + return __rdtime_d (); +} + +__rdtime_t +test_rdtimeh_w () +{ + return __rdtimeh_w (); +} + +__rdtime_t +test_rdtimel_w () +{ + return __rdtimel_w (); +} + +unsigned int +test_movfcsr2gr () +{ + return __movfcsr2gr (1); +} + +void +test_movgr2fcsr (unsigned int _1) +{ + __movgr2fcsr (1, _1); +} + +void +test_dcacop (unsigned long int _1) +{ + __dcacop (1, _1, 1); +} + +unsigned int +test_cpucfg (unsigned int _1) +{ + return __cpucfg (_1); +} + +void +test_asrtle_d (long int _1, long int _2) +{ + __asrtle_d (_1, _2); +} + +void +test_asrtgt_d (long int _1, long int _2) +{ + __asrtgt_d (_1, _2); +} + +long int +test_dlddir (long int _1) +{ + return __dlddir (_1, 1); +} + +void +test_dldpte (long int _1) +{ + __dldpte (_1, 1); +} + +int +test_crc_w_b_w (char _1, int _2) +{ + return __crc_w_b_w (_1, _2); +} + +int +test_crc_w_h_w (short _1, int _2) +{ + return __crc_w_h_w (_1, _2); +} + +int +test_crc_w_w_w (int _1, int _2) +{ + return __crc_w_w_w (_1, _2); +} + +int +test_crc_w_d_w (long int _1, int _2) +{ + return __crc_w_d_w (_1, _2); +} + +int +test_crcc_w_b_w (char _1, int _2) +{ + return __crcc_w_b_w (_1, _2); +} + +int +test_crcc_w_h_w (short _1, int _2) +{ + return __crcc_w_h_w (_1, _2); +} + +int +test_crcc_w_w_w (int _1, int _2) +{ + return __crcc_w_w_w (_1, _2); +} + +int +test_crcc_w_d_w (long int _1, int _2) +{ + return __crcc_w_d_w (_1, _2); +} + +unsigned int +test_csrrd () +{ + return __csrrd (1); +} + +unsigned int +test_csrwr (unsigned int _1) +{ + return __csrwr (_1, 1); +} + +unsigned int +test_csrxchg (unsigned int _1, unsigned int _2) +{ + return __csrxchg (_1, _2, 1); +} + +unsigned long int +test_dcsrrd () +{ + return __dcsrrd (1); +} + +unsigned long int +test_dcsrwr (unsigned long int _1) +{ + return __dcsrwr (_1, 1); +} + +unsigned long int +test_dcsrxchg (unsigned long int _1, unsigned long int _2) +{ + return __dcsrxchg (_1, _2, 1); +} + +unsigned char +test_iocsrrd_b (unsigned int _1) +{ + return __iocsrrd_b (_1); +} + +unsigned char +test_iocsrrd_h (unsigned int _1) +{ + return __iocsrrd_h (_1); +} + +unsigned int +test_iocsrrd_w (unsigned int _1) +{ + return __iocsrrd_w (_1); +} + +unsigned long int +test_iocsrrd_d (unsigned int _1) +{ + return __iocsrrd_d (_1); +} + +void +test_iocsrwr_b (unsigned char _1, unsigned int _2) +{ + __iocsrwr_b (_1, _2); +} + +void +test_iocsrwr_h (unsigned short _1, unsigned int _2) +{ + __iocsrwr_h (_1, _2); +} + +void +test_iocsrwr_w (unsigned int _1, unsigned int _2) +{ + __iocsrwr_w (_1, _2); +} + +void +test_iocsrwr_d (unsigned long int _1, unsigned int _2) +{ + __iocsrwr_d (_1, _2); +} + +void +test_dbar () +{ + __dbar (1); +} + +void +test_ibar () +{ + __ibar (1); +} + +void +test_syscall () +{ + __syscall (1); +} + +void +test_break () +{ + __break (1); +} + +void +test_tlbsrch () +{ + __tlbsrch (); +} + +void +test_tlbrd () +{ + __tlbrd (); +} + +void +test_tlbwr () +{ + __tlbwr (); +} + +void +test_tlbfill () +{ + __tlbfill (); +} + +void +test_tlbclr () +{ + __tlbclr (); +} + +void +test_tlbflush () +{ + __tlbflush (); +} diff --git a/gcc/testsuite/gcc.target/loongarch/loongarch.exp b/gcc/testsuite/gcc.target/loongarch/loongarch.exp new file mode 100644 index 00000000000..41977c8e402 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/loongarch.exp @@ -0,0 +1,40 @@ +# Copyright (C) 2021-2022 Free Software Foundation, Inc. + +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with GCC; see the file COPYING3. If not see +# . + +# GCC testsuite that uses the `dg.exp' driver. + +# Exit immediately if this isn't a LoongArch target. +if ![istarget loongarch*-*-*] then { + return +} + +# Load support procs. +load_lib gcc-dg.exp + +# If a testcase doesn't have special options, use these. +global DEFAULT_CFLAGS +if ![info exists DEFAULT_CFLAGS] then { + set DEFAULT_CFLAGS " " +} + +# Initialize `dg'. +dg-init + +# Main loop. +dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*.\[cS\]]] \ + "" $DEFAULT_CFLAGS +# All done. +dg-finish diff --git a/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c b/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c new file mode 100644 index 00000000000..2e04b99e301 --- /dev/null +++ b/gcc/testsuite/gcc.target/loongarch/tst-asm-const.c @@ -0,0 +1,16 @@ +/* Test asm const. */ +/* { dg-do compile } */ +/* { dg-final { scan-assembler-times "foo:.*\\.long 1061109567.*\\.long 52" 1 } } */ +int foo () +{ + __asm__ volatile ( + "foo:" + "\n\t" + ".long %a0\n\t" + ".long %a1\n\t" + : + :"i"(0x3f3f3f3f), "i"(52) + : + ); +} + diff --git a/gcc/testsuite/go.test/go-test.exp b/gcc/testsuite/go.test/go-test.exp index a402388ee9d..11c178ad7ec 100644 --- a/gcc/testsuite/go.test/go-test.exp +++ b/gcc/testsuite/go.test/go-test.exp @@ -232,6 +232,9 @@ proc go-set-goarch { } { "riscv64-*-*" { set goarch "riscv64" } + "loongarch64-*-*" { + set goarch "loongarch64" + } "s390*-*-*" { if [check_effective_target_ilp32] { set goarch "s390" diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 737e1a8913b..843b508b010 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -286,6 +286,10 @@ proc check_configured_with { pattern } { proc check_weak_available { } { global target_cpu + if { [ string first "loongarch" $target_cpu ] >= 0 } { + return 1 + } + # All mips targets should support it if { [ string first "mips" $target_cpu ] >= 0 } { @@ -1297,6 +1301,14 @@ proc check_effective_target_mpaired_single { } { # Return true if the target has access to FPU instructions. proc check_effective_target_hard_float { } { + if { [istarget loongarch*-*-*] } { + return [check_no_compiler_messages hard_float assembly { + #if (defined __loongarch_soft_float) + #error __loongarch_soft_float + #endif + }] + } + if { [istarget mips*-*-*] } { return [check_no_compiler_messages hard_float assembly { #if (defined __mips_soft_float || defined __mips16) @@ -8616,6 +8628,7 @@ proc check_effective_target_sync_char_short { } { || [istarget cris-*-*] || ([istarget sparc*-*-*] && [check_effective_target_sparc_v9]) || ([istarget arc*-*-*] && [check_effective_target_arc_atomic]) + || [istarget loongarch*-*-*] || [check_effective_target_mips_llsc] }}] } @@ -10708,6 +10721,7 @@ proc check_effective_target_branch_cost {} { || [istarget epiphany*-*-*] || [istarget frv*-*-*] || [istarget i?86-*-*] || [istarget x86_64-*-*] + || [istarget loongarch*-*-*] || [istarget mips*-*-*] || [istarget s390*-*-*] || [istarget riscv*-*-*]