x86: Correct march=sapphirerapids to base on icelake server

  Hi Hongtao,

This patch is to correct march=sapphirerapids to base on icelake server.
and update sapphirerapids in the documentation.

OK for master and backport to GCC 11?


gcc/Changelog:

	PR target/104963
	* config/i386/i386.h (PTA_SAPPHIRERAPIDS): change it to base on ICX.
	* doc/invoke.texi: Update documents for Intel sapphirerapids.

gcc/testsuite/ChangeLog

	PR target/104963
	* gcc.target/i386/pr104963.c: New test case.
---
 gcc/config/i386/i386.h                   |  5 +++--
 gcc/doc/invoke.texi                      | 11 ++++++-----
 gcc/testsuite/gcc.target/i386/pr104963.c | 12 ++++++++++++
 3 files changed, 21 insertions(+), 7 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr104963.c
  

On Fri, Mar 18, 2022 at 11:32 AM Cui,Lili <lili.cui@intel.com> wrote:
>
> Hi Hongtao,
>
> This patch is to correct march=sapphirerapids to base on icelake server.
> and update sapphirerapids in the documentation.
>
> OK for master and backport to GCC 11?
Ok.
>
>
> gcc/Changelog:
>
>         PR target/104963
>         * config/i386/i386.h (PTA_SAPPHIRERAPIDS): change it to base on ICX.
>         * doc/invoke.texi: Update documents for Intel sapphirerapids.
>
> gcc/testsuite/ChangeLog
>
>         PR target/104963
>         * gcc.target/i386/pr104963.c: New test case.
> ---
>  gcc/config/i386/i386.h                   |  5 +++--
>  gcc/doc/invoke.texi                      | 11 ++++++-----
>  gcc/testsuite/gcc.target/i386/pr104963.c | 12 ++++++++++++
>  3 files changed, 21 insertions(+), 7 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr104963.c
>
> diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h
> index 37b523cea4f..b92955177fe 100644
> --- a/gcc/config/i386/i386.h
> +++ b/gcc/config/i386/i386.h
> @@ -2323,10 +2323,11 @@ constexpr wide_int_bitmask PTA_ICELAKE_SERVER = PTA_ICELAKE_CLIENT
>    | PTA_PCONFIG | PTA_WBNOINVD | PTA_CLWB;
>  constexpr wide_int_bitmask PTA_TIGERLAKE = PTA_ICELAKE_CLIENT | PTA_MOVDIRI
>    | PTA_MOVDIR64B | PTA_CLWB | PTA_AVX512VP2INTERSECT | PTA_KL | PTA_WIDEKL;
> -constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_COOPERLAKE | PTA_MOVDIRI
> +constexpr wide_int_bitmask PTA_SAPPHIRERAPIDS = PTA_ICELAKE_SERVER | PTA_MOVDIRI
>    | PTA_MOVDIR64B | PTA_AVX512VP2INTERSECT | PTA_ENQCMD | PTA_CLDEMOTE
>    | PTA_PTWRITE | PTA_WAITPKG | PTA_SERIALIZE | PTA_TSXLDTRK | PTA_AMX_TILE
> -  | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16;
> +  | PTA_AMX_INT8 | PTA_AMX_BF16 | PTA_UINTR | PTA_AVXVNNI | PTA_AVX512FP16
> +  | PTA_AVX512BF16;
>  constexpr wide_int_bitmask PTA_KNL = PTA_BROADWELL | PTA_AVX512PF
>    | PTA_AVX512ER | PTA_AVX512F | PTA_AVX512CD | PTA_PREFETCHWT1;
>  constexpr wide_int_bitmask PTA_BONNELL = PTA_CORE2 | PTA_MOVBE;
> diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
> index d65979bba3f..59baa5e5747 100644
> --- a/gcc/doc/invoke.texi
> +++ b/gcc/doc/invoke.texi
> @@ -31288,11 +31288,12 @@ AVX512VP2INTERSECT and KEYLOCKER instruction set support.
>  Intel sapphirerapids CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3,
>  SSSE3, SSE4.1, SSE4.2, POPCNT, CX16, SAHF, FXSR, AVX, XSAVE, PCLMUL, FSGSBASE,
>  RDRND, F16C, AVX2, BMI, BMI2, LZCNT, FMA, MOVBE, HLE, RDSEED, ADCX, PREFETCHW,
> -AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, CLWB, AVX512VL, AVX512BW,
> -AVX512DQ, AVX512CD, AVX512VNNI, AVX512BF16 MOVDIRI, MOVDIR64B,
> -AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG, SERIALIZE, TSXLDTRK,
> -UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI and AVX512FP16 instruction set
> -support.
> +AES, CLFLUSHOPT, XSAVEC, XSAVES, SGX, AVX512F, AVX512VL, AVX512BW, AVX512DQ,
> +AVX512CD, PKU, AVX512VBMI, AVX512IFMA, SHA, AVX512VNNI, GFNI, VAES, AVX512VBMI2
> +VPCLMULQDQ, AVX512BITALG, RDPID, AVX512VPOPCNTDQ, PCONFIG, WBNOINVD, CLWB,
> +MOVDIRI, MOVDIR64B, AVX512VP2INTERSECT, ENQCMD, CLDEMOTE, PTWRITE, WAITPKG,
> +SERIALIZE, TSXLDTRK, UINTR, AMX-BF16, AMX-TILE, AMX-INT8, AVX-VNNI and
> +AVX512FP16 instruction set support.
>
>  @item alderlake
>  Intel Alderlake CPU with 64-bit extensions, MOVBE, MMX, SSE, SSE2, SSE3, SSSE3,
> diff --git a/gcc/testsuite/gcc.target/i386/pr104963.c b/gcc/testsuite/gcc.target/i386/pr104963.c
> new file mode 100644
> index 00000000000..19000671ebf
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104963.c
> @@ -0,0 +1,12 @@
> +/* PR target/104963 */
> +/* { dg-do compile } */
> +/* { dg-options "-O2 -march=sapphirerapids" } */
> +
> +#include<immintrin.h>
> +
> +__m512i
> +foo (__m512i a, __m512i b)
> +{
> +    return _mm512_permutexvar_epi8(a, b);
> +}
> +
> --
> 2.17.1
>
> Thanks.