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(Coremail) with SMTP id zQCowACn30FlfiFiZUgYAg--.62793S3; Fri, 04 Mar 2022 10:50:31 +0800 (CST) From: yulong@nj.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] RISC-V: Add mininal support for Zicbo[mzp] Date: Fri, 4 Mar 2022 10:49:53 +0800 Message-Id: <20220304024955.25201-2-yulong@nj.iscas.ac.cn> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> References: <20220304024955.25201-1-yulong@nj.iscas.ac.cn> X-CM-TRANSID: zQCowACn30FlfiFiZUgYAg--.62793S3 X-Coremail-Antispam: 1UD129KBjvJXoWxJFy5ZF1UJrWrXF43tw4DCFg_yoW5CF18pF W8WwsxZ34FqFsxWw4xtr18Ga45A3ZYgr1fGF48ur1UAayDX3y8AFn09w13ZrWkXFs8Zrn2 v3Wj9w1Y9w4UCFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 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T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, ptomsich@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, kito.cheng@gmail.com, jiawei@iscas.ac.cn, research_trasio@irq.a4lg.com, wuwei2016@iscas.ac.cn, yulong-plct , shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: yulong-plct This commit adds minimal support for 'Zicbom','Zicboz' and 'Zicbop' extensions. 7 8 gcc/ChangeLog: 9 10 * common/config/riscv/riscv-common.cc: Add zicbom, zicboz, zicbop extensions. 11 * config/riscv/riscv-opts.h (MASK_ZICBOZ): New. 12 (MASK_ZICBOM): New. 13 (MASK_ZICBOP): New. 14 (TARGET_ZICBOZ): New. 15 (TARGET_ZICBOM): New. 16 (TARGET_ZICBOP): New. 17 * config/riscv/riscv.opt: New. --- gcc/common/config/riscv/riscv-common.cc | 6 ++++++ gcc/config/riscv/riscv-opts.h | 9 +++++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 18 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.cc b/gcc/common/config/riscv/riscv-common.cc index a904893b9ed..3ba8f240977 100644 --- a/gcc/common/config/riscv/riscv-common.cc +++ b/gcc/common/config/riscv/riscv-common.cc @@ -164,6 +164,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicboz",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbom",ISA_SPEC_CLASS_NONE, 1, 0}, + {"zicbop",ISA_SPEC_CLASS_NONE, 1, 0}, {"zve32x", ISA_SPEC_CLASS_NONE, 1, 0}, {"zve32f", ISA_SPEC_CLASS_NONE, 1, 0}, @@ -1049,6 +1052,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED}, {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {"zicboz", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOZ}, + {"zicbom", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOM}, + {"zicbop", &gcc_options::x_riscv_zicmo_subext, MASK_ZICBOP}, {"zve32x", &gcc_options::x_target_flags, MASK_VECTOR}, {"zve32f", &gcc_options::x_target_flags, MASK_VECTOR}, diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 929e4e3a7c5..d17cf6ea18a 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,6 +83,15 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZICBOZ (1 << 0) +#define MASK_ZICBOM (1 << 1) +#define MASK_ZICBOP (1 << 2) + + +#define TARGET_ZICBOZ ((riscv_zicmo_subext & MASK_ZICBOZ) != 0) +#define TARGET_ZICBOM ((riscv_zicmo_subext & MASK_ZICBOM) != 0) +#define TARGET_ZICBOP ((riscv_zicmo_subext & MASK_ZICBOP) != 0) + #define MASK_ZBKB (1 << 0) #define MASK_ZBKC (1 << 1) #define MASK_ZBKX (1 << 2) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 9fffc08220d..2058a874d31 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -200,6 +200,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zicmo_subext + TargetVariable int riscv_zk_subext