From patchwork Wed Feb 23 09:44:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Liao Shihua X-Patchwork-Id: 51325 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A082939484B2 for ; Wed, 23 Feb 2022 09:46:24 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTP id 16A2D385DC07 for ; Wed, 23 Feb 2022 09:44:36 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 16A2D385DC07 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [58.212.93.238]) by APP-05 (Coremail) with SMTP id zQCowADXD0L8ARZiCQpOAQ--.41254S3; Wed, 23 Feb 2022 17:44:30 +0800 (CST) From: shihua@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/5 V1] RISC-V:Implement instruction patterns for Crypto extension Date: Wed, 23 Feb 2022 17:44:14 +0800 Message-Id: <20220223094418.3518-2-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20220223094418.3518-1-shihua@iscas.ac.cn> References: <20220223094418.3518-1-shihua@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowADXD0L8ARZiCQpOAQ--.41254S3 X-Coremail-Antispam: 1UD129KBjvAXoW3ZrWUGr4kJFy7JF1kAFy7Wrg_yoW8GFyDKo Z5tr4kJF15JFyF9ws5Ca1fJ34DXr4jyr1xJa9Igw4Fva15trZ8Jr1kGa1a93s3JFsrXa4x Jrn3uF1DJFWkXws7n29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUOF7AC8VAFwI0_Xr0_Wr1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r18M28IrcIa0x kI8VCY1x0267AKxVWUCVW8JwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l84AC jcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr 1l84ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0D M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjx v20xvE14v26r1j6r18McIj6I8E87Iv67AKxVW8JVWxJwAm72CE4IkC6x0Yz7v_Jr0_Gr1l F7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2 IY04v7M4kE6xkIj40Ew7xC0wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8 JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1V AFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xII jxv20xvEc7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4 A2jsIE14v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU 0xZFpf9x0JU45l8UUUUU= X-Originating-IP: [58.212.93.238] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCwcGEVz4k1koYwAAs+ X-Spam-Status: No, score=-13.3 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_SHORT, RCVD_IN_MSPIKE_H5, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ben.marshall@pqshield.com, cmuellner@ventanamicro.com, andrew@sifive.com, jiawei@iscas.ac.cn, mjos@iki.fi, kito.cheng@sifive.com, LiaoShihua Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: LiaoShihua gcc/ChangeLog: * config/riscv/predicates.md (bs_operand): operand for bs (rnum_operand): * config/riscv/riscv.md: include crypto.md * config/riscv/crypto.md: New file. Co-Authored-By: Wu --- gcc/config/riscv/crypto.md | 383 +++++++++++++++++++++++++++++++++ gcc/config/riscv/predicates.md | 8 + gcc/config/riscv/riscv.md | 1 + 3 files changed, 392 insertions(+) create mode 100644 gcc/config/riscv/crypto.md diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md new file mode 100644 index 00000000000..591066fac3b --- /dev/null +++ b/gcc/config/riscv/crypto.md @@ -0,0 +1,383 @@ +;; Machine description for K extension. +;; Copyright (C) 2022 Free Software Foundation, Inc. +;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn) and ShiHua Liao (shihua@iscas.ac.cn). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +(define_c_enum "unspec" [ + ;;ZBKB unspecs + UNSPEC_ROR + UNSPEC_ROL + UNSPEC_BREV8 + UNSPEC_BSWAP + UNSPEC_ZIP + UNSPEC_UNZIP + + ;; Zbkc unspecs + UNSPEC_CLMUL + UNSPEC_CLMULH + + ;; Zbkx unspecs + UNSPEC_XPERM8 + UNSPEC_XPERM4 + + ;; Zknd unspecs + UNSPEC_AES_DSI + UNSPEC_AES_DSMI + UNSPEC_AES_DS + UNSPEC_AES_DSM + UNSPEC_AES_IM + UNSPEC_AES_KS1I + UNSPEC_AES_KS2 + + ;; Zkne unspecs + UNSPEC_AES_ES + UNSPEC_AES_ESM + UNSPEC_AES_ESI + UNSPEC_AES_ESMI + + ;; Zknh unspecs + UNSPEC_SHA_256_SIG0 + UNSPEC_SHA_256_SIG1 + UNSPEC_SHA_256_SUM0 + UNSPEC_SHA_256_SUM1 + UNSPEC_SHA_512_SIG0 + UNSPEC_SHA_512_SIG0H + UNSPEC_SHA_512_SIG0L + UNSPEC_SHA_512_SIG1 + UNSPEC_SHA_512_SIG1H + UNSPEC_SHA_512_SIG1L + UNSPEC_SHA_512_SUM0 + UNSPEC_SHA_512_SUM0R + UNSPEC_SHA_512_SUM1 + UNSPEC_SHA_512_SUM1R + + ;; Zksh + UNSPEC_SM3_P0 + UNSPEC_SM3_P1 + + ;;Zksed + UNSPEC_SM4_ED + UNSPEC_SM4_KS +]) + +(define_insn "riscv_ror_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_ROR))] + "TARGET_ZBKB" + "ror\t%0,%1,%2") + +(define_insn "riscv_rol_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_ROL))] + "TARGET_ZBKB" + "rol\t%0,%1,%2") + +(define_insn "riscv_brev8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_BREV8))] + "TARGET_ZBKB" + "brev8\t%0,%1") + +(define_insn "riscv_bswap" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_BSWAP))] + "TARGET_ZBKB" + "bswap\t%0,%1") + +(define_insn "riscv_zip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_ZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "zip\t%0,%1") + +(define_insn "riscv_unzip" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r")] + UNSPEC_UNZIP))] + "TARGET_ZBKB && !TARGET_64BIT" + "unzip\t%0,%1") + +(define_insn "riscv_clmul_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMUL))] + "TARGET_ZBKC" + "clmul\t%0,%1,%2") + +(define_insn "riscv_clmulh_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_CLMULH))] + "TARGET_ZBKC" + "clmulh\t%0,%1,%2") + +(define_insn "riscv_xperm8_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM8))] + "TARGET_ZBKX" + "xperm8\t%0,%1,%2") + +(define_insn "riscv_xperm4_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r")] + UNSPEC_XPERM4))] + "TARGET_ZBKX" + "xperm4\t%0,%1,%2") + +(define_insn "riscv_aes32dsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_AES_DSI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsi\t%0,%1,%2,%3") + +(define_insn "riscv_aes32dsmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_AES_DSMI))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsmi\t%0,%1,%2,%3") + +(define_insn "riscv_aes64ds" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DS))] + "TARGET_ZKND && TARGET_64BIT" + "aes64ds\t%0,%1,%2") + +(define_insn "riscv_aes64dsm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64dsm\t%0,%1,%2") + +(define_insn "riscv_aes64im" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_AES_IM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64im\t%0,%1") + +(define_insn "riscv_aes64ks1i" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:SI 2 "rnum_operand" "i")] + UNSPEC_AES_KS1I))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks1i\t%0,%1,%2") + +(define_insn "riscv_aes64ks2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_KS2))] + "(TARGET_ZKND || TARGET_ZKNE) && TARGET_64BIT" + "aes64ks2\t%0,%1,%2") + +(define_insn "riscv_aes32esi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_AES_ESI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esi\t%0,%1,%2,%3") + +(define_insn "riscv_aes32esmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_AES_ESMI))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esmi\t%0,%1,%2,%3") + +(define_insn "riscv_aes64es" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64es\t%0,%1,%2") + +(define_insn "riscv_aes64esm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64esm\t%0,%1,%2") + +;; Zknh - SHA256 + +(define_insn "riscv_sha256sig0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG0))] + "TARGET_ZKNH" + "sha256sig0\t%0,%1") + +(define_insn "riscv_sha256sig1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SIG1))] + "TARGET_ZKNH" + "sha256sig1\t%0,%1") + +(define_insn "riscv_sha256sum0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM0))] + "TARGET_ZKNH" + "sha256sum0\t%0,%1") + +(define_insn "riscv_sha256sum1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SHA_256_SUM1))] + "TARGET_ZKNH" + "sha256sum1\t%0,%1") + +(define_insn "riscv_sha512sig0h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0h\t%0,%1,%2") + +(define_insn "riscv_sha512sig0l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG0L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig0l\t%0,%1,%2") + +(define_insn "riscv_sha512sig1h" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1H))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1h\t%0,%1,%2") + +(define_insn "riscv_sha512sig1l" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SIG1L))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sig1l\t%0,%1,%2") + +(define_insn "riscv_sha512sum0r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM0R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum0r\t%0,%1,%2") + +(define_insn "riscv_sha512sum1r" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r")] + UNSPEC_SHA_512_SUM1R))] + "TARGET_ZKNH && !TARGET_64BIT" + "sha512sum1r\t%0,%1,%2") + +(define_insn "riscv_sha512sig0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig0\t%0,%1") + +(define_insn "riscv_sha512sig1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SIG1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sig1\t%0,%1") + +(define_insn "riscv_sha512sum0" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM0))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum0\t%0,%1") + +(define_insn "riscv_sha512sum1" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_SHA_512_SUM1))] + "TARGET_ZKNH && TARGET_64BIT" + "sha512sum1\t%0,%1") + +(define_insn "riscv_sm3p0_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P0))] + "TARGET_ZKSH" + "sm3p0\t%0,%1") + +(define_insn "riscv_sm3p1_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r")] + UNSPEC_SM3_P1))] + "TARGET_ZKSH" + "sm3p1\t%0,%1") + +;; Zksed + +(define_insn "riscv_sm4ed_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_SM4_ED))] + "TARGET_ZKSED" + "sm4ed\t%0,%1,%2,%3") + +(define_insn "riscv_sm4ks_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:X 2 "register_operand" "r") + (match_operand:SI 3 "bs_operand" "i")] + UNSPEC_SM4_KS))] + "TARGET_ZKSED" + "sm4ks\t%0,%1,%2,%3") \ No newline at end of file diff --git a/gcc/config/riscv/predicates.md b/gcc/config/riscv/predicates.md index 97cdbdf053b..7e0e86651c0 100644 --- a/gcc/config/riscv/predicates.md +++ b/gcc/config/riscv/predicates.md @@ -239,3 +239,11 @@ (define_predicate "const63_operand" (and (match_code "const_int") (match_test "INTVAL (op) == 63"))) + +(define_predicate "bs_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) < 4"))) + +(define_predicate "rnum_operand" + (and (match_code "const_int") + (match_test "INTVAL (op) < 11"))) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index b3c5bce842a..59bfecb6341 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2864,6 +2864,7 @@ [(set_attr "length" "12")]) (include "bitmanip.md") +(include "crypto.md") (include "sync.md") (include "peephole.md") (include "pic.md")