[i386] ICE: QImode(not SImode) operand should be passed to gen_vec_initv16qiqi in ashlv16qi3.

Message ID 20220209090308.96206-1-hongtao.liu@intel.com
State New
Headers
Series [i386] ICE: QImode(not SImode) operand should be passed to gen_vec_initv16qiqi in ashlv16qi3. |

Commit Message

Liu, Hongtao Feb. 9, 2022, 9:03 a.m. UTC
  ix86_expand_vector_init expects vals to be a parallel containing
values of individual fields which should be either element mode of the
vector mode, or a vector mode with the same element mode and smaller
number of elements.

But in the expander ashlv16qi3, the second operand is SImode which
can't be directly passed to gen_vec_initv16qiqi.

Bootstrapped on CLX
Regtested on x86_64-pc-linux-gnu{-m32\ -mxop\ -mavx2,\ -mxop\ -mavx2}.
Don't have machine with xop for native bootstrap, but i think the fix
should be ok.

Ok for trunk?

gcc/ChangeLog:

	PR target/104451
	* config/i386/sse.md (<insn><mode>3): lowpart_subreg
	operands[2] from SImode to QImode.

gcc/testsuite/ChangeLog:

	PR target/104451
	* gcc.target/i386/pr104451.c: New test.
---
 gcc/config/i386/sse.md                   |  3 ++-
 gcc/testsuite/gcc.target/i386/pr104451.c | 25 ++++++++++++++++++++++++
 2 files changed, 27 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/pr104451.c
  

Comments

Uros Bizjak Feb. 9, 2022, 9:09 a.m. UTC | #1
On Wed, Feb 9, 2022 at 10:03 AM liuhongt <hongtao.liu@intel.com> wrote:
>
> ix86_expand_vector_init expects vals to be a parallel containing
> values of individual fields which should be either element mode of the
> vector mode, or a vector mode with the same element mode and smaller
> number of elements.
>
> But in the expander ashlv16qi3, the second operand is SImode which
> can't be directly passed to gen_vec_initv16qiqi.
>
> Bootstrapped on CLX
> Regtested on x86_64-pc-linux-gnu{-m32\ -mxop\ -mavx2,\ -mxop\ -mavx2}.
> Don't have machine with xop for native bootstrap, but i think the fix
> should be ok.
>
> Ok for trunk?

Please add -mxop to dg-options of the testcase.

OK with the above change.

Thanks,
Uros.

>
> gcc/ChangeLog:
>
>         PR target/104451
>         * config/i386/sse.md (<insn><mode>3): lowpart_subreg
>         operands[2] from SImode to QImode.
>
> gcc/testsuite/ChangeLog:
>
>         PR target/104451
>         * gcc.target/i386/pr104451.c: New test.
> ---
>  gcc/config/i386/sse.md                   |  3 ++-
>  gcc/testsuite/gcc.target/i386/pr104451.c | 25 ++++++++++++++++++++++++
>  2 files changed, 27 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/pr104451.c
>
> diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
> index d8cb7b65594..36b35f68349 100644
> --- a/gcc/config/i386/sse.md
> +++ b/gcc/config/i386/sse.md
> @@ -24153,8 +24153,9 @@ (define_expand "<insn><mode>3"
>             negate = true;
>         }
>        par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
> +      tmp = lowpart_subreg (QImode, operands[2], SImode);
>        for (i = 0; i < 16; i++)
> -        XVECEXP (par, 0, i) = operands[2];
> +       XVECEXP (par, 0, i) = tmp;
>
>        tmp = gen_reg_rtx (V16QImode);
>        emit_insn (gen_vec_initv16qiqi (tmp, par));
> diff --git a/gcc/testsuite/gcc.target/i386/pr104451.c b/gcc/testsuite/gcc.target/i386/pr104451.c
> new file mode 100644
> index 00000000000..22f3ad092b3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/pr104451.c
> @@ -0,0 +1,25 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx2 -O" } */
> +
> +typedef char __attribute__((__vector_size__ (16))) V;
> +typedef unsigned char __attribute__((__vector_size__ (16))) UV;
> +V v;
> +UV uv;
> +
> +V
> +foo (long c)
> +{
> +  return v << c;
> +}
> +
> +V
> +foo1 (long c)
> +{
> +  return v >> c;
> +}
> +
> +UV
> +foo2 (unsigned long uc)
> +{
> +  return uv >> uc;
> +}
> --
> 2.18.1
>
  

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index d8cb7b65594..36b35f68349 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -24153,8 +24153,9 @@  (define_expand "<insn><mode>3"
 	    negate = true;
 	}
       par = gen_rtx_PARALLEL (V16QImode, rtvec_alloc (16));
+      tmp = lowpart_subreg (QImode, operands[2], SImode);
       for (i = 0; i < 16; i++)
-        XVECEXP (par, 0, i) = operands[2];
+	XVECEXP (par, 0, i) = tmp;
 
       tmp = gen_reg_rtx (V16QImode);
       emit_insn (gen_vec_initv16qiqi (tmp, par));
diff --git a/gcc/testsuite/gcc.target/i386/pr104451.c b/gcc/testsuite/gcc.target/i386/pr104451.c
new file mode 100644
index 00000000000..22f3ad092b3
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr104451.c
@@ -0,0 +1,25 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx2 -O" } */
+
+typedef char __attribute__((__vector_size__ (16))) V;
+typedef unsigned char __attribute__((__vector_size__ (16))) UV;
+V v;
+UV uv;
+
+V
+foo (long c)
+{
+  return v << c;
+}
+
+V
+foo1 (long c)
+{
+  return v >> c;
+}
+
+UV
+foo2 (unsigned long uc)
+{
+  return uv >> uc;
+}