diff mbox series

MIPS: use 8bit for IPL in Cause register

Message ID 20220126032920.1608048-1-yunqiang.su@cipunited.com
State New
Headers
Series MIPS: use 8bit for IPL in Cause register |

Commit Message

YunQiang Su Jan. 26, 2022, 3:29 a.m. UTC 
  Since MIPS r2, the IPL section in Cause register has been expand
to 8bit instead of 6bit.

Since __attribute__((interrupt)) is only supported for r2+,
we don't need to detect the target.

gcc/ChangeLog:

	* config/mips/mips.cc (mips_expand_prologue):
	  IPL is 8bit for r2+.
---
 gcc/config/mips/mips.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Maciej W. Rozycki Jan. 26, 2022, 6:40 p.m. UTC | #1 
On Wed, 26 Jan 2022, YunQiang Su wrote:

> Since MIPS r2, the IPL section in Cause register has been expand
> to 8bit instead of 6bit.

 Hmm, I cannot see it in my copy of the architecture manual I'm afraid.  
The interpretation may have changed, but the field is still 6-bit (not 
counting the software interrupts).  Now the MCU ASE does expand the IPL 
field, but we can't rely on that here, not at least unconditionally, and 
then MCU is MIPSr3+.

 What problem are you trying to solve anyway?

  Maciej
diff mbox series

Patch

diff --git a/gcc/config/mips/mips.cc b/gcc/config/mips/mips.cc
index 4f9683e8bf4..bde88fb8e5a 100644
--- a/gcc/config/mips/mips.cc
+++ b/gcc/config/mips/mips.cc
@@ -12255,7 +12255,7 @@  mips_expand_prologue (void)
 	      if (!cfun->machine->keep_interrupts_masked_p
 		  && cfun->machine->int_mask == INT_MASK_EIC)
 		emit_insn (gen_insvsi (gen_rtx_REG (SImode, K1_REG_NUM),
-				       GEN_INT (6),
+				       GEN_INT (8),
 				       GEN_INT (SR_IPL),
 				       gen_rtx_REG (SImode, K0_REG_NUM)));