Message ID | 20220110062326.31812-1-haochen.jiang@intel.com |
---|---|
State | Committed |
Commit | 4bb79e27c02c5cd57d5781bef20e70982d898c40 |
Headers |
Return-Path: <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id CEA383891C18 for <patchwork@sourceware.org>; Mon, 10 Jan 2022 06:23:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CEA383891C18 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641795839; bh=vKAk41MWuJGrNI0qOHYkoIhw1XiLvlEg6i3pNtOZU/A=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:Cc:From; b=rEYAE7GnRgrJdKTsWgVGwPw5Fuc8ST0/vbR+FtT6iFzRvVFvioQzgnRAqb1sappXJ bhZr8ExRGXdrDVu7358LGIBJRwM3lugTGhIxmA9WteIFGdB5XPrU2QjX7OBajXc57O 7tOeynJlKLcr6+YRGhhH3baVF6bh8jHvopTpt3HA= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by sourceware.org (Postfix) with ESMTPS id 12DD83858402 for <gcc-patches@gcc.gnu.org>; Mon, 10 Jan 2022 06:23:29 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 12DD83858402 X-IronPort-AV: E=McAfee;i="6200,9189,10222"; a="242958249" X-IronPort-AV: E=Sophos;i="5.88,276,1635231600"; d="scan'208";a="242958249" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jan 2022 22:23:29 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,276,1635231600"; d="scan'208";a="528150874" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga008.jf.intel.com with ESMTP; 09 Jan 2022 22:23:28 -0800 Received: from shliclel320.sh.intel.com (shliclel320.sh.intel.com [10.239.236.50]) by scymds01.sc.intel.com with ESMTP id 20A6NRLm032324; Sun, 9 Jan 2022 22:23:27 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Remove register restriction on operands for andnot insn Date: Mon, 10 Jan 2022 14:23:26 +0800 Message-Id: <20220110062326.31812-1-haochen.jiang@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.7 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list <gcc-patches.gcc.gnu.org> List-Unsubscribe: <https://gcc.gnu.org/mailman/options/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe> List-Archive: <https://gcc.gnu.org/pipermail/gcc-patches/> List-Post: <mailto:gcc-patches@gcc.gnu.org> List-Help: <mailto:gcc-patches-request@gcc.gnu.org?subject=help> List-Subscribe: <https://gcc.gnu.org/mailman/listinfo/gcc-patches>, <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe> From: Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> Reply-To: Haochen Jiang <haochen.jiang@intel.com> Cc: hongtao.liu@intel.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" <gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org> |
Series |
[i386] Remove register restriction on operands for andnot insn
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Commit Message
Jiang, Haochen
Jan. 10, 2022, 6:23 a.m. UTC
Hi all, This patch removes the register restriction on operands for andnot insn so that it can be used from memory. Regtested on x86_64-pc-linux-gnu. Ok for trunk? BRs, Haochen gcc/ChangeLog: PR target/53652 * config/i386/sse.md (*andnot<mode>3): Remove register restriction. gcc/testsuite/ChangeLog: PR target/53652 * gcc.target/i386/pr53652-1.c: New test. --- gcc/config/i386/sse.md | 2 +- gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c
Comments
Hi Hongtao, I have changed that message in this patch. Ok for trunk? Thx, Haochen -----Original Message----- From: Hongtao Liu <crazylht@gmail.com> Sent: Monday, January 10, 2022 3:25 PM To: Jiang, Haochen <haochen.jiang@intel.com> Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Liu, Hongtao <hongtao.liu@intel.com> Subject: Re: [PATCH] [i386] Remove register restriction on operands for andnot insn On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi all, > > This patch removes the register restriction on operands for andnot insn so that it can be used from memory. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? > > BRs, > Haochen > > gcc/ChangeLog: > > PR target/53652 > * config/i386/sse.md (*andnot<mode>3): Remove register restriction. It should be "Extend predicate of operands[1] from register_operand to vector_operand". Similar for you commit message. > > gcc/testsuite/ChangeLog: > > PR target/53652 > * gcc.target/i386/pr53652-1.c: New test. > --- > gcc/config/i386/sse.md | 2 +- > gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++ > 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 > gcc/testsuite/gcc.target/i386/pr53652-1.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > 0997d9edf9d..4448b875d35 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -16630,7 +16630,7 @@ > (define_insn "*andnot<mode>3" > [(set (match_operand:VI 0 "register_operand" "=x,x,v") > (and:VI > - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) > + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) > (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] > "TARGET_SSE" > { > diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c > b/gcc/testsuite/gcc.target/i386/pr53652-1.c > new file mode 100644 > index 00000000000..bd07ee29f4d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msse2" } */ > +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */ > +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */ > + > +typedef unsigned long long vec __attribute__((vector_size (16))); vec > +g; vec f1 (vec a, vec b) { > + return ~a&b; > +} > +vec f2 (vec a, vec b) > +{ > + return ~g&b; > +} > + > -- > 2.18.1 >
On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > Hi all, > > This patch removes the register restriction on operands for andnot insn so that it can be used from memory. > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? > > BRs, > Haochen > > gcc/ChangeLog: > > PR target/53652 > * config/i386/sse.md (*andnot<mode>3): Remove register restriction. It should be "Extend predicate of operands[1] from register_operand to vector_operand". Similar for you commit message. > > gcc/testsuite/ChangeLog: > > PR target/53652 > * gcc.target/i386/pr53652-1.c: New test. > --- > gcc/config/i386/sse.md | 2 +- > gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++ > 2 files changed, 17 insertions(+), 1 deletion(-) > create mode 100644 gcc/testsuite/gcc.target/i386/pr53652-1.c > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md > index 0997d9edf9d..4448b875d35 100644 > --- a/gcc/config/i386/sse.md > +++ b/gcc/config/i386/sse.md > @@ -16630,7 +16630,7 @@ > (define_insn "*andnot<mode>3" > [(set (match_operand:VI 0 "register_operand" "=x,x,v") > (and:VI > - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) > + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) > (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] > "TARGET_SSE" > { > diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c b/gcc/testsuite/gcc.target/i386/pr53652-1.c > new file mode 100644 > index 00000000000..bd07ee29f4d > --- /dev/null > +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c > @@ -0,0 +1,16 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -msse2" } */ > +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */ > +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */ > + > +typedef unsigned long long vec __attribute__((vector_size (16))); > +vec g; > +vec f1 (vec a, vec b) > +{ > + return ~a&b; > +} > +vec f2 (vec a, vec b) > +{ > + return ~g&b; > +} > + > -- > 2.18.1 >
On Mon, Jan 10, 2022 at 3:21 PM Jiang, Haochen <haochen.jiang@intel.com> wrote: > > Hi Hongtao, > > I have changed that message in this patch. Ok for trunk? Ok. > > Thx, > Haochen > > -----Original Message----- > From: Hongtao Liu <crazylht@gmail.com> > Sent: Monday, January 10, 2022 3:25 PM > To: Jiang, Haochen <haochen.jiang@intel.com> > Cc: GCC Patches <gcc-patches@gcc.gnu.org>; Liu, Hongtao <hongtao.liu@intel.com> > Subject: Re: [PATCH] [i386] Remove register restriction on operands for andnot insn > > On Mon, Jan 10, 2022 at 2:23 PM Haochen Jiang via Gcc-patches <gcc-patches@gcc.gnu.org> wrote: > > > > Hi all, > > > > This patch removes the register restriction on operands for andnot insn so that it can be used from memory. > > > > Regtested on x86_64-pc-linux-gnu. Ok for trunk? > > > > BRs, > > Haochen > > > > gcc/ChangeLog: > > > > PR target/53652 > > * config/i386/sse.md (*andnot<mode>3): Remove register restriction. > It should be "Extend predicate of operands[1] from register_operand to vector_operand". > Similar for you commit message. > > > > gcc/testsuite/ChangeLog: > > > > PR target/53652 > > * gcc.target/i386/pr53652-1.c: New test. > > --- > > gcc/config/i386/sse.md | 2 +- > > gcc/testsuite/gcc.target/i386/pr53652-1.c | 16 ++++++++++++++++ > > 2 files changed, 17 insertions(+), 1 deletion(-) create mode 100644 > > gcc/testsuite/gcc.target/i386/pr53652-1.c > > > > diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index > > 0997d9edf9d..4448b875d35 100644 > > --- a/gcc/config/i386/sse.md > > +++ b/gcc/config/i386/sse.md > > @@ -16630,7 +16630,7 @@ > > (define_insn "*andnot<mode>3" > > [(set (match_operand:VI 0 "register_operand" "=x,x,v") > > (and:VI > > - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) > > + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) > > (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] > > "TARGET_SSE" > > { > > diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c > > b/gcc/testsuite/gcc.target/i386/pr53652-1.c > > new file mode 100644 > > index 00000000000..bd07ee29f4d > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c > > @@ -0,0 +1,16 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -msse2" } */ > > +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */ > > +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */ > > + > > +typedef unsigned long long vec __attribute__((vector_size (16))); vec > > +g; vec f1 (vec a, vec b) { > > + return ~a&b; > > +} > > +vec f2 (vec a, vec b) > > +{ > > + return ~g&b; > > +} > > + > > -- > > 2.18.1 > > > > > -- > BR, > Hongtao
diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 0997d9edf9d..4448b875d35 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -16630,7 +16630,7 @@ (define_insn "*andnot<mode>3" [(set (match_operand:VI 0 "register_operand" "=x,x,v") (and:VI - (not:VI (match_operand:VI 1 "register_operand" "0,x,v")) + (not:VI (match_operand:VI 1 "vector_operand" "0,x,v")) (match_operand:VI 2 "bcst_vector_operand" "xBm,xm,vmBr")))] "TARGET_SSE" { diff --git a/gcc/testsuite/gcc.target/i386/pr53652-1.c b/gcc/testsuite/gcc.target/i386/pr53652-1.c new file mode 100644 index 00000000000..bd07ee29f4d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr53652-1.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -msse2" } */ +/* { dg-final { scan-assembler-times "pandn\[ \\t\]" 2 } } */ +/* { dg-final { scan-assembler-not "vpternlogq\[ \\t\]" } } */ + +typedef unsigned long long vec __attribute__((vector_size (16))); +vec g; +vec f1 (vec a, vec b) +{ + return ~a&b; +} +vec f2 (vec a, vec b) +{ + return ~g&b; +} +