From patchwork Thu Jan 6 09:21:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 49616 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id A1A223858D39 for ; Thu, 6 Jan 2022 09:22:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org A1A223858D39 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1641460947; bh=02fbs80a692u40JqfAaI0pwGIIZ/txuh/Bi63GzDct4=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=BA74P5wZcNIgwP3bnVhsIEbw4Tk+5yCEKT6BuqcCcUcRY8OdsW7VPWOv/H0GikWKy DdG8uLQmCXsz/X04P+Ydh4njC3gp3OLgfv2hLg+LYIr96yIfbjKFuBdr5lcxp8WtMI 1BwCmDPGiimH3XVXP+oGFeWl1hTpEgsfzKfDww7s= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by sourceware.org (Postfix) with ESMTPS id D8C1C385AC28 for ; Thu, 6 Jan 2022 09:21:22 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D8C1C385AC28 X-IronPort-AV: E=McAfee;i="6200,9189,10217"; a="229951076" X-IronPort-AV: E=Sophos;i="5.88,266,1635231600"; d="scan'208";a="229951076" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jan 2022 01:21:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,266,1635231600"; d="scan'208";a="574714660" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga008.fm.intel.com with ESMTP; 06 Jan 2022 01:21:04 -0800 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 2069L2C6003067; Thu, 6 Jan 2022 01:21:03 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Optimize V16HF vector insert to element 0 for AVX2. Date: Thu, 6 Jan 2022 17:21:02 +0800 Message-Id: <20220106092102.32982-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, DKIMWL_WL_HIGH, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Also remove mode attribute blendsuf, use ssemodesuf instead. Bootstrapped and regtested on x86_64-pc-linux-gnu{-m32,}. Ready to push to trunk. gcc/ChangeLog: PR target/103753 * config/i386/i386-expand.c (ix86_expand_vector_set): Not use gen_avx2_pblendph_pblendd when elt == 0. * config/i386/sse.md (avx2_pblendph): Rename to .. (avx2_pblend_pblendd).. this, and extend to V16HI. (*avx2_pblendw): Rename to .. (*avx2_pblend): .. this, and extend to V16HF. (avx2_pblendw): Rename to .. (*avx2_pblend): .. this, and extend to V16HF. (blendsuf): Removed. (sse4_1_pblend): Renamed to .. (sse4_1_pblend): .. this. gcc/testsuite/ChangeLog: * gcc.target/i386/pr103753.c: New test. --- gcc/config/i386/i386-expand.c | 5 ++- gcc/config/i386/sse.md | 48 +++++++++++------------- gcc/testsuite/gcc.target/i386/pr103753.c | 17 +++++++++ 3 files changed, 42 insertions(+), 28 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr103753.c diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index e93ef1cafa6..0d219d6bb69 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -16245,10 +16245,11 @@ ix86_expand_vector_set (bool mmx_ok, rtx target, rtx val, int elt) goto half; case E_V16HFmode: - if (TARGET_AVX2) + /* For ELT == 0, vec_setv8hf_0 can save 1 vpbroadcastw. */ + if (TARGET_AVX2 && elt != 0) { mmode = SImode; - gen_blendm = gen_avx2_pblendph; + gen_blendm = gen_avx2_pblendph_pblendd; blendm_const = true; break; } diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 033b60d9aa2..c986c73bef8 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -21291,10 +21291,7 @@ (define_insn_and_split "*_pblendvb_lt_subreg_not" (lt:VI1_AVX2 (match_dup 3) (match_dup 4))] UNSPEC_BLENDV))] "operands[3] = gen_lowpart (mode, operands[3]);") -(define_mode_attr blendsuf - [(V8HI "w") (V8HF "ph")]) - -(define_insn "sse4_1_pblend" +(define_insn "sse4_1_pblend" [(set (match_operand:V8_128 0 "register_operand" "=Yr,*x,x") (vec_merge:V8_128 (match_operand:V8_128 2 "vector_operand" "YrBm,*xBm,xm") @@ -21313,11 +21310,11 @@ (define_insn "sse4_1_pblend" (set_attr "mode" "TI")]) ;; The builtin uses an 8-bit immediate. Expand that. -(define_expand "avx2_pblendw" - [(set (match_operand:V16HI 0 "register_operand") - (vec_merge:V16HI - (match_operand:V16HI 2 "nonimmediate_operand") - (match_operand:V16HI 1 "register_operand") +(define_expand "avx2_pblend" + [(set (match_operand:V16_256 0 "register_operand") + (vec_merge:V16_256 + (match_operand:V16_256 2 "nonimmediate_operand") + (match_operand:V16_256 1 "register_operand") (match_operand:SI 3 "const_0_to_255_operand")))] "TARGET_AVX2" { @@ -21325,11 +21322,11 @@ (define_expand "avx2_pblendw" operands[3] = GEN_INT (val << 8 | val); }) -(define_expand "avx2_pblendph" - [(set (match_operand:V16HF 0 "register_operand") - (vec_merge:V16HF - (match_operand:V16HF 2 "register_operand") - (match_operand:V16HF 1 "register_operand") +(define_expand "avx2_pblend_pblendd" + [(set (match_operand:V16_256 0 "register_operand") + (vec_merge:V16_256 + (match_operand:V16_256 2 "register_operand") + (match_operand:V16_256 1 "register_operand") (match_operand:SI 3 "const_int_operand")))] "TARGET_AVX2 && !((INTVAL (operands[3]) & 0xff) && (INTVAL (operands[3]) & 0xff00))" @@ -21339,7 +21336,7 @@ (define_expand "avx2_pblendph" emit_move_insn (operands[0], operands[1]); else { - rtx tmp = gen_reg_rtx (V16HImode); + rtx tmp = gen_reg_rtx (mode); rtx blendw_idx, blendd_idx; if (mask & 0xff) @@ -21352,13 +21349,12 @@ (define_expand "avx2_pblendph" blendw_idx = GEN_INT (mask >> 8 & 0xff); blendd_idx = GEN_INT (240); } - operands[1] = lowpart_subreg (V16HImode, operands[1], V16HFmode); - operands[2] = lowpart_subreg (V16HImode, operands[2], V16HFmode); - emit_insn (gen_avx2_pblendw (tmp, operands[1], operands[2], blendw_idx)); + emit_insn (gen_avx2_pblend (tmp, operands[1], + operands[2], blendw_idx)); - operands[0] = lowpart_subreg (V8SImode, operands[0], V16HFmode); - tmp = lowpart_subreg (V8SImode, tmp, V16HImode); - operands[1] = lowpart_subreg (V8SImode, operands[1], V16HImode); + operands[0] = lowpart_subreg (V8SImode, operands[0], mode); + tmp = lowpart_subreg (V8SImode, tmp, mode); + operands[1] = lowpart_subreg (V8SImode, operands[1], mode); emit_insn (gen_avx2_pblenddv8si (operands[0], operands[1], tmp, blendd_idx)); } @@ -21366,11 +21362,11 @@ (define_expand "avx2_pblendph" DONE; }) -(define_insn "*avx2_pblendw" - [(set (match_operand:V16HI 0 "register_operand" "=x") - (vec_merge:V16HI - (match_operand:V16HI 2 "nonimmediate_operand" "xm") - (match_operand:V16HI 1 "register_operand" "x") +(define_insn "*avx2_pblend" + [(set (match_operand:V16_256 0 "register_operand" "=x") + (vec_merge:V16_256 + (match_operand:V16_256 2 "nonimmediate_operand" "xm") + (match_operand:V16_256 1 "register_operand" "x") (match_operand:SI 3 "avx2_pblendw_operand" "n")))] "TARGET_AVX2" { diff --git a/gcc/testsuite/gcc.target/i386/pr103753.c b/gcc/testsuite/gcc.target/i386/pr103753.c new file mode 100644 index 00000000000..4b2b3e46d8b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr103753.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx2 -mno-avx512f -O2" } */ +/* { dg-final { scan-assembler-not "vpbroadcastw" } } */ + +typedef _Float16 __v16hf __attribute__ ((__vector_size__ (32))); + +__v16hf foo (_Float16 x) +{ + return (__v16hf) { x, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f, 0.0f }; +} + +typedef short __v16hi __attribute__ ((__vector_size__ (32))); + +__v16hi bar (short x) +{ + return (__v16hi) { x, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; +}