diff mbox series

[Gimple] Fix ICE. [PR103682]

Message ID 20211214051723.62082-1-hongtao.liu@intel.com
State Committed
Commit a2a0c91b47537b16908981e206f4e42db8425eca
Headers
Series [Gimple] Fix ICE. [PR103682] |

Commit Message

Liu, Hongtao Dec. 14, 2021, 5:17 a.m. UTC 
  > This testcase should just go in gcc.c-torture/compile and remove the
> dg-options too.
> The main reason there is nothing specific to x86 here.
>
Thanks, here's the updated patch.


Check is_gimple_assign before gimple_assign_rhs_code.

gcc/ChangeLog:

	PR target/103682
	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
	is_gimple_assign before gimple_assign_rhs_code.

gcc/testsuite/ChangeLog:

	* gcc.c-torture/compile/pr103682.c: New test.
---
 gcc/testsuite/gcc.c-torture/compile/pr103682.c | 3 +++
 gcc/tree-ssa-ccp.c                             | 4 ++--
 2 files changed, 5 insertions(+), 2 deletions(-)
 create mode 100644 gcc/testsuite/gcc.c-torture/compile/pr103682.c

Comments

Jeff Law Dec. 14, 2021, 6:42 p.m. UTC | #1 
On 12/13/2021 10:17 PM, liuhongt via Gcc-patches wrote:
>> This testcase should just go in gcc.c-torture/compile and remove the
>> dg-options too.
>> The main reason there is nothing specific to x86 here.
>>
> Thanks, here's the updated patch.
>
>
> Check is_gimple_assign before gimple_assign_rhs_code.
>
> gcc/ChangeLog:
>
> 	PR target/103682
> 	* tree-ssa-ccp.c (optimize_atomic_bit_test_and): Check
> 	is_gimple_assign before gimple_assign_rhs_code.
>
> gcc/testsuite/ChangeLog:
>
> 	* gcc.c-torture/compile/pr103682.c: New test.
OK
jeff
diff mbox series

Patch

diff --git a/gcc/testsuite/gcc.c-torture/compile/pr103682.c b/gcc/testsuite/gcc.c-torture/compile/pr103682.c
new file mode 100644
index 00000000000..5ee4b21f7e6
--- /dev/null
+++ b/gcc/testsuite/gcc.c-torture/compile/pr103682.c
@@ -0,0 +1,3 @@ 
+int bug(unsigned *ready, unsigned u) {
+  return __atomic_fetch_and (ready, ~u, 0) & u;
+}
diff --git a/gcc/tree-ssa-ccp.c b/gcc/tree-ssa-ccp.c
index 9e12da8f011..a5b1f60f979 100644
--- a/gcc/tree-ssa-ccp.c
+++ b/gcc/tree-ssa-ccp.c
@@ -3703,8 +3703,8 @@  optimize_atomic_bit_test_and (gimple_stmt_iterator *gsip,
 	      g = SSA_NAME_DEF_STMT (mask);
 	    }
 
-	  rhs_code = gimple_assign_rhs_code (g);
-	  if (rhs_code != LSHIFT_EXPR
+	  if (!is_gimple_assign (g)
+	      || gimple_assign_rhs_code (g) != LSHIFT_EXPR
 	      || !integer_onep (gimple_assign_rhs1 (g)))
 	    return;
 	  bit = gimple_assign_rhs2 (g);