From patchwork Mon Dec 6 03:41:01 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 48523 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id C79A73858426 for ; Mon, 6 Dec 2021 03:41:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C79A73858426 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638762098; bh=LNGYnzajcDk/N64dYYTR/qAZb/j6svzxn4PwwJPDido=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=NE2iXfE1kRkDjkx4WOZhwGnyacjtX+ZRFkfM8NoxcoLsHFWfSn/Da4CdYbaZ5CX2l tw20JzmJwRpMoyHczkbOhOag91JXwxJt7au53+nD9enA3j6HPK7TtzI8ocQ63yL8om IrvFC5TIo8twXvqkdDiwyVbVQXNoXLiHfnyPoGbM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by sourceware.org (Postfix) with ESMTPS id 83385385841D for ; Mon, 6 Dec 2021 03:41:05 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 83385385841D X-IronPort-AV: E=McAfee;i="6200,9189,10189"; a="234756076" X-IronPort-AV: E=Sophos;i="5.87,290,1631602800"; d="scan'208";a="234756076" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Dec 2021 19:41:04 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,290,1631602800"; d="scan'208";a="678834967" Received: from scymds01.sc.intel.com ([10.148.94.138]) by orsmga005.jf.intel.com with ESMTP; 05 Dec 2021 19:41:03 -0800 Received: from shliclel057.sh.intel.com (shliclel057.sh.intel.com [10.239.236.57]) by scymds01.sc.intel.com with ESMTP id 1B63f2xx015853; Sun, 5 Dec 2021 19:41:02 -0800 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Prefer INT_SSE_REGS for SSE_FLOAT_MODE_P in preferred_reload_class. Date: Mon, 6 Dec 2021 11:41:01 +0800 Message-Id: <20211206034101.1663134-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.2 MIME-Version: 1.0 X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" When moves between integer and sse registers are cheap. 2021-12-06 Hongtao Liu Uroš Bizjak gcc/ChangeLog: PR target/95740 * config/i386/i386.c (ix86_preferred_reload_class): Allow integer regs when moves between register units are cheap. * config/i386/i386.h (INT_SSE_CLASS_P): New. gcc/testsuite/ChangeLog: * gcc.target/i386/pr95740.c: New test. --- gcc/config/i386/i386.c | 12 ++++++++++-- gcc/config/i386/i386.h | 2 ++ gcc/testsuite/gcc.target/i386/pr95740.c | 26 +++++++++++++++++++++++++ 3 files changed, 38 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr95740.c diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 80fee627358..e3c2e294988 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -19194,9 +19194,17 @@ ix86_preferred_reload_class (rtx x, reg_class_t regclass) return NO_REGS; } - /* Prefer SSE regs only, if we can use them for math. */ + /* Prefer SSE if we can use them for math. Also allow integer regs + when moves between register units are cheap. */ if (SSE_FLOAT_MODE_P (mode) && TARGET_SSE_MATH) - return SSE_CLASS_P (regclass) ? regclass : NO_REGS; + { + if (TARGET_INTER_UNIT_MOVES_FROM_VEC + && TARGET_INTER_UNIT_MOVES_TO_VEC + && GET_MODE_SIZE (mode) <= GET_MODE_SIZE (word_mode)) + return INT_SSE_CLASS_P (regclass) ? regclass : NO_REGS; + else + return SSE_CLASS_P (regclass) ? regclass : NO_REGS; + } /* Generally when we see PLUS here, it's the function invariant (plus soft-fp const_int). Which can only be computed into general diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 2fda1e0686e..ec90e47904b 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -1283,6 +1283,8 @@ enum reg_class reg_class_subset_p ((CLASS), FLOAT_REGS) #define SSE_CLASS_P(CLASS) \ reg_class_subset_p ((CLASS), ALL_SSE_REGS) +#define INT_SSE_CLASS_P(CLASS) \ + reg_class_subset_p ((CLASS), INT_SSE_REGS) #define MMX_CLASS_P(CLASS) \ ((CLASS) == MMX_REGS) #define MASK_CLASS_P(CLASS) \ diff --git a/gcc/testsuite/gcc.target/i386/pr95740.c b/gcc/testsuite/gcc.target/i386/pr95740.c new file mode 100644 index 00000000000..7ecd71ba8c1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr95740.c @@ -0,0 +1,26 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-msse2 -O2 -mtune=generic -mtune-ctrl=use_incdec -masm=att -mfpmath=sse" } */ +/* { dg-final { scan-assembler-times {(?n)movd[\t ]*%xmm0.*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incl[\t ]*%eax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)movq[\t ]*%xmm0.*%rax} 1 } } */ +/* { dg-final { scan-assembler-times {(?n)incq[\t ]*%rax} 1 } } */ + +int +foo (float a) +{ + union{ + int b; + float a;}u; + u.a = a; + return u.b + 1; +} + +long long +foo1 (double a) +{ + union{ + long long b; + double a;}u; + u.a = a; + return u.b + 1; +}