From patchwork Thu Dec 2 14:44:45 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Iain Buclaw X-Patchwork-Id: 48393 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 874EE385BF86 for ; Thu, 2 Dec 2021 14:45:24 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 874EE385BF86 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1638456324; bh=eKXgUq/yBagRr78jDHnvixrpN2O/GLpSzgMTSasS6lU=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=gg8NqZ26HBZZvlUGv3XCUDHZQzXuqZGX1uhqT/sXLyABs7j6UdAor+guz9ZEt/fwy 7aAkzCzTXtm6GyeBZSsA/vZyth9mPCwynRCeCO8qBSvxbXaWboh0F/kuWp2J88RmHC sH0DtAuXXhGZpWlNSPd9jPguwHfXPbDv7PmNzvDw= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mout-p-202.mailbox.org (mout-p-202.mailbox.org [IPv6:2001:67c:2050::465:202]) by sourceware.org (Postfix) with ESMTPS id 2C66C385840F for ; Thu, 2 Dec 2021 14:44:55 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2C66C385840F Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-p-202.mailbox.org (Postfix) with ESMTPS id 4J4dyq24qRzQjmd; Thu, 2 Dec 2021 15:44:51 +0100 (CET) X-Virus-Scanned: amavisd-new at heinlein-support.de To: gcc-patches@gcc.gnu.org Subject: [committed] libphobos: Push all callee-save registers on the stack before GC scan on ARM Date: Thu, 2 Dec 2021 15:44:45 +0100 Message-Id: <20211202144445.466341-1-ibuclaw@gdcproject.org> MIME-Version: 1.0 X-Spam-Status: No, score=-14.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, RCVD_IN_DNSWL_LOW, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Iain Buclaw via Gcc-patches From: Iain Buclaw Reply-To: Iain Buclaw Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi, This is the library fix for PR103520 that also prevents the garbage collector from releasing live memory. However this requires that the host compiler has been patched with this fix, so the GC will remain disabled in the D front-end for now until enough time has passed for this to have trickled down into enough releases. Bootstrapped and regression tested on aarch64-linux-gnu, committed to mainline and backported to the release branches. Regards, Iain --- libphobos/ChangeLog: * libdruntime/core/thread/osthread.d (callWithStackShell): Push all callee-save registers on the stack for AArch64 and ARM. --- libphobos/libdruntime/core/thread/osthread.d | 29 ++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/libphobos/libdruntime/core/thread/osthread.d b/libphobos/libdruntime/core/thread/osthread.d index 653adb91a7d..c9bc1305ad0 100644 --- a/libphobos/libdruntime/core/thread/osthread.d +++ b/libphobos/libdruntime/core/thread/osthread.d @@ -1487,6 +1487,35 @@ in (fn) }} sp = cast(void*)®s[0]; } + else version (AArch64) + { + // Callee-save registers, x19-x28 according to AAPCS64, section + // 5.1.1. Include x29 fp because it optionally can be a callee + // saved reg + size_t[11] regs = void; + // store the registers in pairs + asm pure nothrow @nogc + { + "stp x19, x20, %0" : "=m" (regs[ 0]), "=m" (regs[1]); + "stp x21, x22, %0" : "=m" (regs[ 2]), "=m" (regs[3]); + "stp x23, x24, %0" : "=m" (regs[ 4]), "=m" (regs[5]); + "stp x25, x26, %0" : "=m" (regs[ 6]), "=m" (regs[7]); + "stp x27, x28, %0" : "=m" (regs[ 8]), "=m" (regs[9]); + "str x29, %0" : "=m" (regs[10]); + "mov %0, sp" : "=r" (sp); + } + } + else version (ARM) + { + // Callee-save registers, according to AAPCS, section 5.1.1. + // arm and thumb2 instructions + size_t[8] regs = void; + asm pure nothrow @nogc + { + "stm %0, {r4-r11}" : : "r" (regs.ptr) : "memory"; + "mov %0, sp" : "=r" (sp); + } + } else { __builtin_unwind_init();