From patchwork Sat Nov 27 08:27:35 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lulu Cheng X-Patchwork-Id: 48215 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 71B62385AC12 for ; Sat, 27 Nov 2021 08:31:58 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from loongson.cn (mail.loongson.cn [114.242.206.163]) by sourceware.org (Postfix) with ESMTP id 0E3E23857836 for ; Sat, 27 Nov 2021 08:28:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0E3E23857836 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=loongson.cn Received: from 5.5.5 (unknown [10.2.5.5]) by mail.loongson.cn (Coremail) with SMTP id AQAAf9Dx78oK7KFhnLkAAA--.2037S14; Sat, 27 Nov 2021 16:28:35 +0800 (CST) From: chenglulu To: gcc-patches@gcc.gnu.org Subject: [PATCH 12/12] LoongArch Port: Add doc. Date: Sat, 27 Nov 2021 16:27:35 +0800 Message-Id: <20211127082735.4139682-13-chenglulu@loongson.cn> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20211127082735.4139682-1-chenglulu@loongson.cn> References: <20211127082735.4139682-1-chenglulu@loongson.cn> MIME-Version: 1.0 X-CM-TRANSID: AQAAf9Dx78oK7KFhnLkAAA--.2037S14 X-Coremail-Antispam: 1UD129KBjvAXoW3Aw4kWryrJFW5XrWxXFy3CFg_yoW8GFW5to WSyFWUXayxCr43WrWvkw1kKryUXryfuw1xZFn5Ars0qF1DXay5Aa9xuw1UJay3JFs7Wry8 C348AasayFWxXF13n29KB7ZKAUJUUUUr529EdanIXcx71UUUUU7v73VFW2AGmfu7bjvjm3 AaLaJ3UjIYCTnIWjp_UUUO57AC8VAFwI0_Wr0E3s1l1xkIjI8I6I8E6xAIw20EY4v20xva j40_Wr0E3s1l1IIY67AEw4v_Jr0_Jr4l82xGYIkIc2x26280x7IE14v26r126s0DM28Irc Ia0xkI8VCY1x0267AKxVW5JVCq3wA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK021l 84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26F4j6r 4UJwA2z4x0Y4vEx4A2jsIE14v26r4UJVWxJr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4U JVWxJr1ln4kS14v26r1Y6r17M2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64 kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm 72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYx C7MxkIecxEwVCm-wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s02 6c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF 0_Jw1lIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVW8JVW5JwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67 AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuY vjfU5mhFUUUUU X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yangyujie@loongson.cn, xuchenghua@loongson.cn, chenglulu@loongson.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" * contrib/config-list.mk: Add LoongArch triplet. * gcc/doc/install.texi: Add LoongArch options section. * gcc/doc/invoke.texi: Add LoongArch options section. * gcc/doc/md.texi: Add LoongArch options section. --- contrib/config-list.mk | 5 +- gcc/doc/install.texi | 47 +++++++++- gcc/doc/invoke.texi | 201 +++++++++++++++++++++++++++++++++++++++++ gcc/doc/md.texi | 55 +++++++++++ 4 files changed, 302 insertions(+), 6 deletions(-) diff --git a/contrib/config-list.mk b/contrib/config-list.mk index 3e1d1321861..ba6f12e4693 100644 --- a/contrib/config-list.mk +++ b/contrib/config-list.mk @@ -57,7 +57,10 @@ LIST = aarch64-elf aarch64-linux-gnu aarch64-rtems \ i686-wrs-vxworksae \ i686-cygwinOPT-enable-threads=yes i686-mingw32crt ia64-elf \ ia64-freebsd6 ia64-linux ia64-hpux ia64-hp-vms iq2000-elf lm32-elf \ - lm32-rtems lm32-uclinux m32c-rtems m32c-elf m32r-elf m32rle-elf \ + lm32-rtems lm32-uclinux \ + loongarch64-linux-gnu loongarch64-linux-gnuf64 \ + loongarch64-linux-gnuf32 loongarch64-linux-gnusf \ + m32c-rtems m32c-elf m32r-elf m32rle-elf \ m68k-elf m68k-netbsdelf \ m68k-uclinux m68k-linux m68k-rtems \ mcore-elf microblaze-linux microblaze-elf \ diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 094469b9a4e..90049fc0994 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -733,9 +733,9 @@ Here are the possible CPU types: @quotation aarch64, aarch64_be, alpha, alpha64, amdgcn, arc, arceb, arm, armeb, avr, bfin, bpf, cr16, cris, csky, epiphany, fido, fr30, frv, ft32, h8300, hppa, hppa2.0, -hppa64, i486, i686, ia64, iq2000, lm32, m32c, m32r, m32rle, m68k, mcore, -microblaze, microblazeel, mips, mips64, mips64el, mips64octeon, mips64orion, -mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2, +hppa64, i486, i686, ia64, iq2000, lm32, loongarch64, m32c, m32r, m32rle, m68k, +mcore, microblaze, microblazeel, mips, mips64, mips64el, mips64octeon, +mips64orion, mips64vr, mipsel, mipsisa32, mipsisa32r2, mipsisa64, mipsisa64r2, mipsisa64r2el, mipsisa64sb1, mipsisa64sr71k, mipstx39, mmix, mn10300, moxie, msp430, nds32be, nds32le, nios2, nvptx, or1k, pdp11, powerpc, powerpc64, powerpc64le, powerpcle, pru, riscv32, riscv32be, riscv64, riscv64be, rl78, rx, @@ -1152,8 +1152,9 @@ sysv, aix. @itemx --without-multilib-list Specify what multilibs to build. @var{list} is a comma separated list of values, possibly consisting of a single value. Currently only implemented -for aarch64*-*-*, arm*-*-*, riscv*-*-*, sh*-*-* and x86-64-*-linux*. The -accepted values and meaning for each target is given below. +for aarch64*-*-*, arm*-*-*, loongarch64-*-*, riscv*-*-*, sh*-*-* and +x86-64-*-linux*. The accepted values and meaning for each target is given +below. @table @code @item aarch64*-*-* @@ -1240,6 +1241,14 @@ profile. The union of these options is considered when specifying both @code{-mfloat-abi=hard} @end multitable +@item loongarch*-*-* +@var{list} is a comma-separated list of the following ABI identifiers: +@code{lp64d[/base]} @code{lp64f[/base]} @code{lp64d[/base]}, where the +@code{/base} suffix may be omitted, to enable their respective run-time +libraries. If @var{list} is empty, @code{default} +or @option{--with-multilib-list} is not specified, then the default ABI +as specified by @option{--with-abi} or implied by @option{--target} is selected. + @item riscv*-*-* @var{list} is a single ABI name. The target architecture must be either @code{rv32gc} or @code{rv64gc}. This will build a single multilib for the @@ -4406,6 +4415,34 @@ This configuration is intended for embedded systems. Lattice Mico32 processor. This configuration is intended for embedded systems running uClinux. +@html +
+@end html +@anchor{loongarch} +@heading LoongArch +LoongArch processor. +The following LoongArch targets are available: +@table @code +@item loongarch64-linux-gnu* +LoongArch processor running GNU/Linux. This target triplet may be coupled +with a small set of possible suffixes to identify their default ABI type: +@table @code +@item f64 +Uses @code{lp64d/base} ABI by default. +@item f32 +Uses @code{lp64f/base} ABI by default. +@item sf +Uses @code{lp64s/base} ABI by default. +@end table + +@item loongarch64-linux-gnu +Same as @code{loongarch64-linux-gnuf64}, but may be used with +@option{--with-abi=*} to configure the default ABI type. +@end table + +More information about LoongArch can be found at +@uref{https://github.com/loongson/LoongArch-Documentation}. + @html
@end html diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 3bddfbaae6a..65e8aa7ef2c 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -990,6 +990,16 @@ Objective-C and Objective-C++ Dialects}. @gccoptlist{-mbarrel-shift-enabled -mdivide-enabled -mmultiply-enabled @gol -msign-extend-enabled -muser-enabled} +@emph{LoongArch Options} +@gccoptlist{-march=@var{cpu-type} -mtune=@var{cpu-type} -mabi=@var{base-abi-type} @gol +-mfpu=@var{fpu-type} -msoft-float -msingle-float -mdouble-float @gol +-mbranch-cost=@var{n} -mcheck-zero-division -mno-check-zero-division @gol +-mcond-move-int -mno-cond-move-int @gol +-mcond-move-float -mno-cond-move-float @gol +-memcpy -mno-memcpy -mstrict-align @gol +-mmax-inline-memcpy-size=@var{n} @gol +-mlra -mcmodel=@var{code-model}} + @emph{M32R/D Options} @gccoptlist{-m32r2 -m32rx -m32r @gol -mdebug @gol @@ -18587,6 +18597,7 @@ platform. * HPPA Options:: * IA-64 Options:: * LM32 Options:: +* LoongArch Options:: * M32C Options:: * M32R/D Options:: * M680x0 Options:: @@ -24078,6 +24089,196 @@ Enable user-defined instructions. @end table +@node LoongArch Options +@subsection LoongArch Options +@cindex LoongArch Options + +These command-line options are defined for LoongArch targets: + +@table @gcctabopt +@item -march=@var{cpu-type} +@opindex -march +Generate instructions for the machine type @var{cpu-type}. In contrast to +@option{-mtune=@var{cpu-type}}, which merely tunes the generated code +for the specified @var{cpu-type}, @option{-march=@var{cpu-type}} allows GCC +to generate code that may not run at all on processors other than the one +indicated. Specifying @option{-march=@var{cpu-type}} implies +@option{-mtune=@var{cpu-type}}, except where noted otherwise. + +The choices for @var{cpu-type} are: + +@table @samp +@item native +This selects the CPU to generate code for at compilation time by determining +the processor type of the compiling machine. Using @option{-march=native} +enables all instruction subsets supported by the local machine (hence +the result might not run on different machines). Using @option{-mtune=native} +produces code optimized for the local machine under the constraints +of the selected instruction set. +@item loongarch64 +A generic CPU with 64-bit extensions. +@item la464 +LoongArch LA464 CPU with LBT, LSX, LASX, LVZ. +@end table + + +@item -mtune=@var{cpu-type} +@opindex mtune +Optimize the output for the given processor, specified by microarchitecture +name. + +@item -mabi=@var{base-abi-type} +@opindex mabi +Generate code for the specified calling convention. @gol +Set base ABI to one of: @gol +@table @samp +@item lp64d +Uses 64-bit general purpose registers and 32/64-bit floating-point +registers for parameter passing. Data model is LP64, where int +is 32 bits, while long int and pointers are 64 bits. +@item lp64f +Uses 64-bit general purpose registers and 32-bit floating-point +registers for parameter passing. Data model is LP64, where int +is 32 bits, while long int and pointers are 64 bits. +@item lp64s +Uses 64-bit general purpose registers and no floating-point +registers for parameter passing. Data model is LP64, where int +is 32 bits, while long int and pointers are 64 bits. +@end table + + +@item -mfpu=@var{fpu-type} +@opindex mfpu +Generating code for the specified FPU type: @gol +@table @samp +@item 64 +Allow the use of hardware floating-point instructions for 32-bit +and 64-bit operations. +@item 32 +Allow the use of hardware floating-point instructions for 32-bit +operations. +@item none +@item 0 +Prevent the use of hardware floating-point instructions. +@end table + + +@item -msoft-float +@opindex msoft-float +Force @option{-mfpu=none} and prevents the use of floating-point +registers for parameter passing. This option may change the target +ABI. + +@item -msingle-float +@opindex -msingle-float +Force @option{-mfpu=32} and allow the use of 32-bit floating-point +registers for parameter passing. This option may change the target +ABI. + +@item -mdouble-float +@opindex -mdouble-float +Force @option{-mfpu=64} and allow the use of 32/64-bit floating-point +registers for parameter passing. This option may change the target +ABI. + + +@item -mbranch-cost=@var{n} +@opindex -mbranch-cost +Set the cost of branches to roughly n instructions. + +@item -mcheck-zero-division +@itemx -mno-check-zero-divison +@opindex -mcheck-zero-division +Trap (do not trap) on integer division by zero. The default is '-mcheck-zero- +division'. + + +@item -mcond-move-int +@itemx -mno-cond-move-int +@opindex -mcond-move-int +Conditional moves for floating point are enabled (disabled). The default is +'-mcond-move-float'. + +@item -mmemcpy +@itemx -mno-memcpy +@opindex -mmemcpy +Force (do not force) the use of memcpy for non-trivial block moves. The default +is '-mno-memcpy', which allows GCC to inline most constant-sized copies. + + +@item -mlra +@opindex -mlra +Use the new LRA register allocator. By default, the LRA is used. + +@item -mstrict-align +@itemx -mno-strict-align +@opindex -mstrict-align +Avoid or allow generating memory accesses that may not be aligned on a natural +object boundary as described in the architecture specification. + +@item -msmall-data-limit=@var{number} +@opindex -msmall-data-limit +Put global and static data smaller than @code{number} bytes into a special section (on some targets). +Default value is 0. + + +@item -mmax-inline-memcpy-size=@var{n} +@opindex -mmax-inline-memcpy-size +Set the max size n of memcpy to inline, default n is 1024. + +@item -mcmodel=@var{code-model} +Default code model is normal. +Set the code model to one of: +@table @samp +@item tiny-static +@itemize @bullet +@item +local symbol and global strong symbol: The data section must be within +/-2MiB addressing space. +The text section must be within +/-128MiB addressing space. +@item +global weak symbol: The got table must be within +/-2GiB addressing space. +@end itemize + +@item tiny +@itemize @bullet +@item +local symbol: The data section must be within +/-2MiB addressing space. +The text section must be within +/-128MiB +addressing space. +@item +global symbol: The got table must be within +/-2GiB addressing space. +@end itemize + +@item normal +@itemize @bullet +@item +local symbol: The data section must be within +/-2GiB addressing space. +The text section must be within +/-128MiB addressing space. +@item +global symbol: The got table must be within +/-2GiB addressing space. +@end itemize + +@item large +@itemize @bullet +@item +local symbol: The data section must be within +/-2GiB addressing space. +The text section must be within +/-128GiB addressing space. +@item +global symbol: The got table must be within +/-2GiB addressing space. +@end itemize + +@item extreme(Not implemented yet) +@itemize @bullet +@item +local symbol: The data and text section must be within +/-8EiB addressing space. +@item +global symbol: The data got table must be within +/-8EiB addressing space. +@end itemize +@end table +@end table + + + @node M32C Options @subsection M32C Options @cindex M32C options diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 589f841ea74..ad9d786b1ca 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -2747,6 +2747,61 @@ Memory addressed using the small base register ($sb). $r1h @end table +@item LoongArch---@file{config/loongarch/constraints.md} +@table @code +@item a +A constant call global and noplt address. +@item c +A constant call local address. +@item e +A register that is used as function call. +@item f +A floating-point register (if available). +@item h +A constant call plt address. +@item j +A rester that is used as sibing call. +@item l +A signed 16-bit constant. +@item m +A memory operand whose address is formed by a base register and offset +that is suitable for use in instructions with the same addressing mode +as @code{st.w} and @code{ld.w}. +@item q +A general-purpose register except for $r0 and $r1 for csr instructions. +@item t +A constant call weak address. +@item u +A signed 52bit constant and low 32-bit is zero (for logic instructions). +@item v +A nsigned 64-bit constant and low 44-bit is zero (for logic instructions). +@item z +A floating-point condition code register. +@item G +Floating-point zero. +@item I +A signed 12-bit constant (for arithmetic instructions). +@item J +Integer zero. +@item K +An unsigned 12-bit constant (for logic instructions). +@item Q +A 12-bit constant used for logical operations. +@item W +A memory address based on a member of @code{BASE_REG_CLASS}. This is +true for allreferences. +@item Yd +A constant @code{move_operand} that can be safely loaded using +@code{la}. +@item ZB +An address that is held in a general-purpose register. +The offset is zero. +@item ZC +A memory operand whose address is formed by a base register and offset +that is suitable for use in instructions with the same addressing mode +as @code{ll.w} and @code{sc.w}. +@end table + @item MicroBlaze---@file{config/microblaze/constraints.md} @table @code @item d