From patchwork Mon Nov 22 08:19:09 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: siyu@isrc.iscas.ac.cn X-Patchwork-Id: 47989 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id AFC173858023 for ; Mon, 22 Nov 2021 08:20:02 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 7F76F385841D for ; Mon, 22 Nov 2021 08:19:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 7F76F385841D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=isrc.iscas.ac.cn Authentication-Results: sourceware.org; spf=none smtp.mailfrom=isrc.iscas.ac.cn Received: from localhost.localdomain (unknown [221.216.137.254]) by APP-01 (Coremail) with SMTP id qwCowACHUCN+Upthw+cjCA--.62405S3; Mon, 22 Nov 2021 16:19:10 +0800 (CST) From: siyu@isrc.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 1/2] RISC-V: Add option defines for Scalar Cryptography Date: Mon, 22 Nov 2021 16:19:09 +0800 Message-Id: <20211122081910.1545117-2-siyu@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211122081910.1545117-1-siyu@isrc.iscas.ac.cn> References: <20211122081910.1545117-1-siyu@isrc.iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowACHUCN+Upthw+cjCA--.62405S3 X-Coremail-Antispam: 1UD129KBjvJXoWxAF1fGr48Cr4rKr1rJrWfAFb_yoWrZw4Upa y8Wa1avw1FqF43Wa1ftry8u34Yyw1rGr1fJF47Ww4UAayUJw48A3Wv9w4a9rykXF4FvF92 y3WUG34Y9a4UCrDanT9S1TB71UUUUUJqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUHm14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_Cr1U M2kKe7AKxVWUXVWUAwAS0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4 xG6I80ewAv7VC0I7IYx2IY67AKxVWUXVWUAwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCa FVCjc4AY6r1j6r4UM4x0Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI4 02YVCY1x02628vn2kIc2xKxwAKzVCY07xG64k0F24lc7CjxVAaw2AFwI0_JF0_Jw1lc2xS Y4AK67AK6r43MxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I 8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUtVW8 ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1I6r4UMIIF0xvE2Ix0cI8IcVCY1x 0267AKxVW8JVWxJwCI42IY6xAIw20EY4v20xvaj40_Jr0_JF4lIxAIcVC2z280aVAFwI0_ Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8JrUvcSsGvfC2KfnxnUUI43ZEXa7sRi GQ6JUUUUU== X-Originating-IP: [221.216.137.254] X-CM-SenderInfo: pvl13qplvuuh5lvft2wodfhubq/1tbiBgkNCl0TfxeccwABsA X-Spam-Status: No, score=-10.6 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ben.marshall@pqshield.com, cmuellner@ventanamicro.com, andrew@sifive.com, Richard.Newell@microchip.com, jiawei@iscas.ac.cn, mjos@pqshield.com, kito.cheng@sifive.com, jimw@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: SiYu Wu gcc/ChangeLog: 2021-11-21 SiYu Wu * common/config/riscv/riscv-common.c (riscv_ext_version_table): Add zbk* and zk*. * config/riscv/riscv-opts.h (MASK_ZBKB): New. (MASK_ZBKC): Ditto. (MASK_ZBKX): Ditto. (MASK_ZKNE): Ditto. (MASK_ZKND): Ditto. (MASK_ZKNH): Ditto. (MASK_ZKR): Ditto. (MASK_ZKSED): Ditto. (MASK_ZKSH): Ditto. (MASK_ZKT): Ditto. (TARGET_ZBKB): Ditto. (TARGET_ZBKC): Ditto. (TARGET_ZBKX): Ditto. (TARGET_ZKNE): Ditto. (TARGET_ZKND): Ditto. (TARGET_ZKNH): Ditto. (TARGET_ZKR): Ditto. (TARGET_ZKSED): Ditto. (TARGET_ZKSH): Ditto. (TARGET_ZKT): Ditto. * config/riscv/riscv.opt (riscv_zk_subext): New. --- gcc/common/config/riscv/riscv-common.c | 22 ++++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 22 ++++++++++++++++++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 47 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index b8dd0aeac3e..14dc6057ecd 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -106,6 +106,17 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkb", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkc", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zbkx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkne", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zknd", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zknh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkr", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zksh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkt", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -915,6 +926,17 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zbkb", &gcc_options::x_riscv_zk_subext, MASK_ZBKB}, + {"zbkc", &gcc_options::x_riscv_zk_subext, MASK_ZBKC}, + {"zbkx", &gcc_options::x_riscv_zk_subext, MASK_ZBKX}, + {"zknd", &gcc_options::x_riscv_zk_subext, MASK_ZKND}, + {"zkne", &gcc_options::x_riscv_zk_subext, MASK_ZKNE}, + {"zknh", &gcc_options::x_riscv_zk_subext, MASK_ZKNH}, + {"zkr", &gcc_options::x_riscv_zk_subext, MASK_ZKR}, + {"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED}, + {"zksh", &gcc_options::x_riscv_zk_subext, MASK_ZKSH}, + {"zkt", &gcc_options::x_riscv_zk_subext, MASK_ZKT}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b80f1f..f65ff678811 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,26 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZBKB (1 << 0) +#define MASK_ZBKC (1 << 1) +#define MASK_ZBKX (1 << 2) +#define MASK_ZKNE (1 << 3) +#define MASK_ZKND (1 << 4) +#define MASK_ZKNH (1 << 5) +#define MASK_ZKR (1 << 6) +#define MASK_ZKSED (1 << 7) +#define MASK_ZKSH (1 << 8) +#define MASK_ZKT (1 << 9) + +#define TARGET_ZBKB ((riscv_zk_subext & MASK_ZBKB) != 0) +#define TARGET_ZBKC ((riscv_zk_subext & MASK_ZBKC) != 0) +#define TARGET_ZBKX ((riscv_zk_subext & MASK_ZBKX) != 0) +#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0) +#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0) +#define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0) +#define TARGET_ZKR ((riscv_zk_subext & MASK_ZKR) != 0) +#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0) +#define TARGET_ZKSH ((riscv_zk_subext & MASK_ZKSH) != 0) +#define TARGET_ZKT ((riscv_zk_subext & MASK_ZKT) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e17c2..617000975bf 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zk_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):