From patchwork Fri Nov 5 13:00:57 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 47106 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BABB0385E448 for ; Fri, 5 Nov 2021 13:03:14 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp21.cstnet.cn [159.226.251.21]) by sourceware.org (Postfix) with ESMTP id 414B43858D28 for ; Fri, 5 Nov 2021 13:01:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 414B43858D28 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [120.25.159.94]) by APP-01 (Coremail) with SMTP id qwCowAB3ECEYK4VhkKOhBg--.16147S3; Fri, 05 Nov 2021 21:01:14 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 1/3] RISC-V: Minimal support of zfinx extension Date: Fri, 5 Nov 2021 21:00:57 +0800 Message-Id: <20211105130059.3332-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211105130059.3332-1-jiawei@iscas.ac.cn> References: <20211105130059.3332-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3ECEYK4VhkKOhBg--.16147S3 X-Coremail-Antispam: 1UD129KBjvJXoWxuF4ktFy8AFWDGr1DKry5twb_yoW5uw17pF WrWw45A34Fqan3Wa1xtrW8W3yUJwnYgr1rJw4ku347AanrJrWDAFn09w1Svr4kXFWYvrn2 k3WFk3yYvw4UGa7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBE14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r4j6ryUM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oVCq3wAS 0I0E0xvYzxvE52x082IY62kv0487Mc02F40EFcxC0VAKzVAqx4xG6I80ewAv7VC0I7IYx2 IY67AKxVWUGVWUXwAv7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0 Y48IcxkI7VAKI48JM4x0x7Aq67IIx4CEVc8vx2IErcIFxwACI402YVCY1x02628vn2kIc2 xKxwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v2 6r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2 Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_ Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMI IF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUSYLPUUUUU = X-Originating-IP: [120.25.159.94] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCQcQAF02arV46gAAs4 X-Spam-Status: No, score=-12.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: tariq.kurd@huawei.com, cmuellner@ventanamicro.com, andrew@sifive.com, sinan@isrc.iscas.ac.cn, philipp.tomsich@vrull.eu, jiawei , nelson.chu@sifive.com, kito.cheng@sifive.com, shihua@iscas.ac.cn Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Minimal support of zfinx extension, include 'zfinx' and 'zdinx' corresponding to 'f' and 'd', the 'zdinx' will imply 'zfinx' same as 'd' imply 'f'. gcc/ChangeLog: * common/config/riscv/riscv-common.c(riscv_implied_info_t): Add zdinx imply zfinx. (riscv_ext_version_table): Add zfinx, zdinx. * config/riscv/arch-canonicalize(IMPLIED_EXT): Add zdinx imply zfinx. * config/riscv/riscv-opts.h (MASK_ZFINX): New. (MASK_ZDINX): Ditto. (TARGET_ZFINX): Ditto. (TARGET_ZDINX): Ditto. * config/riscv/riscv.opt(riscv_zf_subext): New. Co-Authored-By: sinan --- gcc/common/config/riscv/riscv-common.c | 7 +++++++ gcc/config/riscv/arch-canonicalize | 1 + gcc/config/riscv/riscv-opts.h | 6 ++++++ gcc/config/riscv/riscv.opt | 3 +++ 4 files changed, 17 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 37b6ea80086..6db5a434257 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -50,6 +50,7 @@ static const riscv_implied_info_t riscv_implied_info[] = {"d", "f"}, {"f", "zicsr"}, {"d", "zicsr"}, + {"zdinx", "zfinx"}, {NULL, NULL} }; @@ -106,6 +107,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -916,6 +920,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/arch-canonicalize b/gcc/config/riscv/arch-canonicalize index c7df3c8a313..9197163d1c3 100755 --- a/gcc/config/riscv/arch-canonicalize +++ b/gcc/config/riscv/arch-canonicalize @@ -36,6 +36,7 @@ LONG_EXT_PREFIXES = ['z', 's', 'h', 'x'] # IMPLIED_EXT = { "d" : ["f"], + "zdinx" : ["zfinx"], } def arch_canonicalize(arch): diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b80f1f..5a790a028cf 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,10 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 1) + +#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e17c2..54d27747eff 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zf_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):