From patchwork Thu Nov 4 06:45:10 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 47029 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 82C18385841C for ; Thu, 4 Nov 2021 06:46:43 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 82C18385841C DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1636008403; bh=/u2Fvse/gdUYbC4M0A4SyFJUfJPODjJTn1jWn5rbNIU=; h=To:Subject:Date:In-Reply-To:References:List-Id:List-Unsubscribe: List-Archive:List-Post:List-Help:List-Subscribe:From:Reply-To: From; b=iiTo0U+LMx7/awIHMqBJZgjs/VttC/dUC8BWuB15CTYiBmNcsHViq0W/tiJNnvCLD K1KaB5dlnwGYgUFSvhW0o03geYcniDgP1i+/N5FqfdOJ158AGdz9fAgc24X6PenWzL t3CHXrCgZ1129XQUb65i6GVOt74+hnO4JOGry31A= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by sourceware.org (Postfix) with ESMTPS id 0291C3858409 for ; Thu, 4 Nov 2021 06:45:15 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 0291C3858409 X-IronPort-AV: E=McAfee;i="6200,9189,10157"; a="255294090" X-IronPort-AV: E=Sophos;i="5.87,208,1631602800"; d="scan'208";a="255294090" Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2021 23:45:15 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.87,208,1631602800"; d="scan'208";a="578462363" Received: from scymds01.sc.intel.com ([10.148.94.138]) by FMSMGA003.fm.intel.com with ESMTP; 03 Nov 2021 23:45:14 -0700 Received: from shliclel051.sh.intel.com (shliclel051.sh.intel.com [10.239.236.51]) by scymds01.sc.intel.com with ESMTP id 1A46jB3R026053; Wed, 3 Nov 2021 23:45:13 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH 2/2] [i386] Extend vternlog define_insn_and_split to memory_operand to enable more optimziation. Date: Thu, 4 Nov 2021 14:45:10 +0800 Message-Id: <20211104064510.93649-2-hongtao.liu@intel.com> X-Mailer: git-send-email 2.18.1 In-Reply-To: <20211104064510.93649-1-hongtao.liu@intel.com> References: <20211104064510.93649-1-hongtao.liu@intel.com> X-Spam-Status: No, score=-11.5 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Bootstrapped and regtested on x86-64-pc-linux-gnu{-m32,}. Ready to push to trunk after first patch is approved. gcc/ChangeLog: PR target/101989 * config/i386/predicates.md (reg_or_notreg_operand): Rename to .. (regmem_or_bitnot_regmem_operand): .. and extend to handle memory_operand. * config/i386/sse.md (*_vpternlog_1): Force_reg the operands which are required to be register_operand. (*_vpternlog_2): Ditto. (*_vpternlog_3): Ditto. (*_vternlog_all): Disallow embeded broadcast for vector HFmodes since it's not a real AVX512FP16 instruction. gcc/testsuite/ChangeLog: * gcc.target/i386/pr101989-3.c: New test. --- gcc/config/i386/predicates.md | 6 ++-- gcc/config/i386/sse.md | 41 +++++++++++++++------- gcc/testsuite/gcc.target/i386/pr101989-3.c | 40 +++++++++++++++++++++ 3 files changed, 72 insertions(+), 15 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr101989-3.c diff --git a/gcc/config/i386/predicates.md b/gcc/config/i386/predicates.md index df5acb425d4..114d8d448f1 100644 --- a/gcc/config/i386/predicates.md +++ b/gcc/config/i386/predicates.md @@ -1046,10 +1046,10 @@ (define_predicate "reg_or_pm1_operand" ;; True for registers, or (not: registers). Used to optimize 3-operand ;; bitwise operation. -(define_predicate "reg_or_notreg_operand" - (ior (match_operand 0 "register_operand") +(define_predicate "regmem_or_bitnot_regmem_operand" + (ior (match_operand 0 "nonimmediate_operand") (and (match_code "not") - (match_test "register_operand (XEXP (op, 0), mode)")))) + (match_test "nonimmediate_operand (XEXP (op, 0), mode)")))) ;; True if OP is acceptable as operand of DImode shift expander. (define_predicate "shiftdi_operand" diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 2764a250229..5aeb6065f13 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -11655,7 +11655,11 @@ (define_insn "*_vternlog_all" (match_operand:V 3 "bcst_vector_operand" "vmBr") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_VTERNLOG))] - "TARGET_AVX512F" + "TARGET_AVX512F +/* Disallow embeded broadcast for vector HFmode since + it's not real AVX512FP16 instruction. */ + && (GET_MODE_SIZE (GET_MODE_INNER (mode)) >= 4 + || GET_CODE (operands[3]) != VEC_DUPLICATE)" "vpternlog\t{%4, %3, %2, %0|%0, %2, %3, %4}" [(set_attr "type" "sselog") (set_attr "prefix" "evex") @@ -11683,11 +11687,11 @@ (define_insn_and_split "*_vpternlog_1" [(set (match_operand:V 0 "register_operand") (any_logic:V (any_logic1:V - (match_operand:V 1 "reg_or_notreg_operand") - (match_operand:V 2 "reg_or_notreg_operand")) + (match_operand:V 1 "regmem_or_bitnot_regmem_operand") + (match_operand:V 2 "regmem_or_bitnot_regmem_operand")) (any_logic2:V - (match_operand:V 3 "reg_or_notreg_operand") - (match_operand:V 4 "reg_or_notreg_operand"))))] + (match_operand:V 3 "regmem_or_bitnot_regmem_operand") + (match_operand:V 4 "regmem_or_bitnot_regmem_operand"))))] "( == 64 || TARGET_AVX512VL) && ix86_pre_reload_split () && (rtx_equal_p (STRIP_UNARY (operands[1]), @@ -11756,6 +11760,10 @@ (define_insn_and_split "*_vpternlog_1" operands[1] = STRIP_UNARY (operands[1]); operands[2] = STRIP_UNARY (operands[2]); operands[6] = STRIP_UNARY (operands[6]); + if (!register_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); + if (!register_operand (operands[6], mode)) + operands[6] = force_reg (mode, operands[6]); operands[5] = GEN_INT (reg_mask); }) @@ -11764,10 +11772,10 @@ (define_insn_and_split "*_vpternlog_2" (any_logic:V (any_logic1:V (any_logic2:V - (match_operand:V 1 "reg_or_notreg_operand") - (match_operand:V 2 "reg_or_notreg_operand")) - (match_operand:V 3 "reg_or_notreg_operand")) - (match_operand:V 4 "reg_or_notreg_operand")))] + (match_operand:V 1 "regmem_or_bitnot_regmem_operand") + (match_operand:V 2 "regmem_or_bitnot_regmem_operand")) + (match_operand:V 3 "regmem_or_bitnot_regmem_operand")) + (match_operand:V 4 "regmem_or_bitnot_regmem_operand")))] "( == 64 || TARGET_AVX512VL) && ix86_pre_reload_split () && (rtx_equal_p (STRIP_UNARY (operands[1]), @@ -11837,15 +11845,20 @@ (define_insn_and_split "*_vpternlog_2" operands[2] = STRIP_UNARY (operands[2]); operands[6] = STRIP_UNARY (operands[6]); operands[5] = GEN_INT (reg_mask); + if (!register_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); + if (!register_operand (operands[6], mode)) + operands[6] = force_reg (mode, operands[6]); + }) (define_insn_and_split "*_vpternlog_3" [(set (match_operand:V 0 "register_operand") (any_logic:V (any_logic1:V - (match_operand:V 1 "reg_or_notreg_operand") - (match_operand:V 2 "reg_or_notreg_operand")) - (match_operand:V 3 "reg_or_notreg_operand")))] + (match_operand:V 1 "regmem_or_bitnot_regmem_operand") + (match_operand:V 2 "regmem_or_bitnot_regmem_operand")) + (match_operand:V 3 "regmem_or_bitnot_regmem_operand")))] "( == 64 || TARGET_AVX512VL) && ix86_pre_reload_split ()" "#" @@ -11876,6 +11889,10 @@ (define_insn_and_split "*_vpternlog_3" operands[2] = STRIP_UNARY (operands[2]); operands[3] = STRIP_UNARY (operands[3]); operands[4] = GEN_INT (reg_mask); + if (!register_operand (operands[2], mode)) + operands[2] = force_reg (mode, operands[2]); + if (!register_operand (operands[3], mode)) + operands[3] = force_reg (mode, operands[3]); }) diff --git a/gcc/testsuite/gcc.target/i386/pr101989-3.c b/gcc/testsuite/gcc.target/i386/pr101989-3.c new file mode 100644 index 00000000000..dfd89918c17 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101989-3.c @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl" } */ +/* { dg-final { scan-assembler-times "vpternlog" 5 } } */ +/* { dg-final { scan-assembler-not "vpxor" } } */ +/* { dg-final { scan-assembler-not "vpor" } } */ +/* { dg-final { scan-assembler-not "vpand" } } */ + +#include + +extern __m256i src1, src2, src3; + +__m256i +foo (void) +{ + return (src2 & ~src1) | (src3 & src1); +} + +__m256i +foo1 (void) +{ + return (src2 & src1) | (src3 & ~src1); +} + +__m256i +foo2 (void) +{ + return (src2 & src1) | (~src3 & src1); +} + +__m256i +foo3 (void) +{ + return (~src2 & src1) | (src3 & src1); +} + +__m256i +foo4 (void) +{ + return src3 & src2 ^ src1; +}