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Sun, 31 Oct 2021 17:34:46 +0800 (CST) From: siyu@isrc.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 03/21] [crypto]: add machine description for Zknd and Zkne Date: Sun, 31 Oct 2021 17:34:27 +0800 Message-Id: <20211031093445.1414518-4-siyu@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211031093445.1414518-1-siyu@isrc.iscas.ac.cn> References: <20211031093445.1414518-1-siyu@isrc.iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3QCM1Y35h2GgQBg--.15675S5 X-Coremail-Antispam: 1UD129KBjvJXoW3Ar4ftF1xXFWrKF18Xr1fJFb_yoW3GFW5p3 98Cw45Ary8ZFsIgayxKFW8Jw15Awn7KF4Y9as5WrZFk3yDX34UAw1vkasIqa4DWa1Yvr47 Za1Sk3yj9w45GaUanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmG14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JrWl82xGYIkIc2 x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UM2 8EF7xvwVC2z280aVAFwI0_Gr0_Cr1l84ACjcxK6I8E87Iv6xkF7I0E14v26r4UJVWxJr1l e2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E2Ix0cI 8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJVW8JwAC jcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2Y2ka0x kIwI1lw4CEc2x0rVAKj4xxMxkIecxEwVAFwVW8uwCF04k20xvY0x0EwIxGrwCFx2IqxVCF s4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r 1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWU JVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1UMIIF0xvE42xK8VAvwI8IcIk0rV WUJVWUCwCI42IY6I8E87Iv67AKxVW8JVWxJwCI42IY6I8E87Iv6xkF7I0E14v26r4UJVWx JrUvcSsGvfC2KfnxnUUI43ZEXa7VUbcyCJUUUUU== X-Originating-IP: [221.216.140.210] X-CM-SenderInfo: pvl13qplvuuh5lvft2wodfhubq/1tbiCwcLClz4kjGDtgAAs- X-Spam-Status: No, score=-8.1 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ben.marshall@pqshield.com, cmuellner@ventanamicro.com, andrew@sifive.com, Richard.Newell@microchip.com, jiawei@iscas.ac.cn, mjos@pqshield.com, kito.cheng@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: SiYu Wu --- gcc/common/config/riscv/riscv-common.c | 6 ++ gcc/config/riscv/crypto.md | 129 +++++++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 6 ++ gcc/config/riscv/riscv.md | 2 + gcc/config/riscv/riscv.opt | 3 + 5 files changed, 146 insertions(+) create mode 100644 gcc/config/riscv/crypto.md diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 37b6ea80086..1e81847ee5c 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zkne", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zknd", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zknd", &gcc_options::x_riscv_zk_subext, MASK_ZKND}, + {"zkne", &gcc_options::x_riscv_zk_subext, MASK_ZKNE}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md new file mode 100644 index 00000000000..170be7ff56c --- /dev/null +++ b/gcc/config/riscv/crypto.md @@ -0,0 +1,129 @@ +;; Machine description for K extension. +;; Copyright (C) 2021 Free Software Foundation, Inc. +;; Contributed by SiYu Wu (siyu@isrc.iscas.ac.cn). + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +(define_c_enum "unspec" [ + ;; Crypto extension unspecs. + UNSPEC_AES_DS + UNSPEC_AES_DSM + UNSPEC_AES_ES + UNSPEC_AES_ESM + UNSPEC_AES_IM + UNSPEC_AES_KS1 + UNSPEC_AES_KS2 +]) + + +;; Zkne&Zknd - AES (RV32) + +(define_insn "riscv_aes32dsi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "immediate_operand" "")] + UNSPEC_AES_DS))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsi\t%0,%1,%2,%3") + +(define_insn "riscv_aes32dsmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "immediate_operand" "")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && !TARGET_64BIT" + "aes32dsmi\t%0,%1,%2,%3") + +(define_insn "riscv_aes32esi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "") + (match_operand:SI 3 "immediate_operand" "")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esi\t%0,%1,%2,%3") + +(define_insn "riscv_aes32esmi" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:SI 1 "register_operand" "r") + (match_operand:SI 2 "register_operand" "r") + (match_operand:SI 3 "immediate_operand" "")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && !TARGET_64BIT" + "aes32esmi\t%0,%1,%2,%3") + + +;; Zkne&Zknd - AES (RV64) + +(define_insn "riscv_aes64ds" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DS))] + "TARGET_ZKND && TARGET_64BIT" + "aes64ds\t%0,%1,%2") + +(define_insn "riscv_aes64dsm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_DSM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64dsm\t%0,%1,%2") + +(define_insn "riscv_aes64es" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ES))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64es\t%0,%1,%2") + +(define_insn "riscv_aes64esm" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_ESM))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64esm\t%0,%1,%2") + +(define_insn "riscv_aes64im" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r")] + UNSPEC_AES_IM))] + "TARGET_ZKND && TARGET_64BIT" + "aes64im\t%0,%1") + +(define_insn "riscv_aes64ks1i" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "immediate_operand" "")] + UNSPEC_AES_KS1))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64ks1i\t%0,%1,%2") + +(define_insn "riscv_aes64ks2" + [(set (match_operand:DI 0 "register_operand" "=r") + (unspec:DI [(match_operand:DI 1 "register_operand" "r") + (match_operand:DI 2 "register_operand" "r")] + UNSPEC_AES_KS2))] + "TARGET_ZKNE && TARGET_64BIT" + "aes64ks2\t%0,%1,%2") + diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b80f1f..b0226335c4f 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,10 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZKNE (1 << 5) +#define MASK_ZKND (1 << 6) + +#define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0) +#define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index 1a786f31258..f95505d07da 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -2765,6 +2765,8 @@ (define_insn "stack_tie" [(set_attr "length" "0")] ) +(include "crypto.md") + ;; This fixes a failure with gcc.c-torture/execute/pr64242.c at -O2 for a ;; 32-bit target when using -mtune=sifive-7-series. The first sched pass ;; runs before register elimination, and we have a non-obvious dependency diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e17c2..617000975bf 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zk_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):