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Sun, 31 Oct 2021 17:34:48 +0800 (CST) From: siyu@isrc.iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: [PATCH 09/21] [crypto]: add machine description for Zksed Date: Sun, 31 Oct 2021 17:34:33 +0800 Message-Id: <20211031093445.1414518-10-siyu@isrc.iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211031093445.1414518-1-siyu@isrc.iscas.ac.cn> References: <20211031093445.1414518-1-siyu@isrc.iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: qwCowAB3QCM1Y35h2GgQBg--.15675S11 X-Coremail-Antispam: 1UD129KBjvJXoWxAr15WFW8WF4kJw1fKrW3Jrb_yoW5WF18pa 95Gw45A34rZFsxWa1ftrW0g345Awn3Gr15CF4ku3yDA3y5X3y8AFnF934a9ryDXF45Zr17 Aa4Fk34j93yUGrJanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUQ014x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_JF0E3s1l82xGYI kIc2x26xkF7I0E14v26ryj6s0DM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2 z4x0Y4vE2Ix0cI8IcVAFwI0_Gr0_Xr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr1j6F 4UJwA2z4x0Y4vEx4A2jsIE14v26r4j6F4UM28EF7xvwVC2z280aVCY1x0267AKxVW8Jr0_ Cr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6x IIjxv20xvE14v26r106r15McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_ Gr1lF7xvr2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8c xan2IY04v7M4kE6xkIj40Ew7xC0wCY02Avz4vE14v_GFWl42xK82IYc2Ij64vIr41l4I8I 3I0E4IkC6x0Yz7v_Jr0_Gr1lx2IqxVAqx4xG67AKxVWUJVWUGwC20s026x8GjcxK67AKxV WUGVWUWwC2zVAF1VAY17CE14v26r1q6r43MIIYrxkI7VAKI48JMIIF0xvE2Ix0cI8IcVAF wI0_Gr0_Xr1lIxAIcVC0I7IYx2IY6xkF7I0E14v26r4UJVWxJr1lIxAIcVCF04k26cxKx2 IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r4j6F4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_ Gr1j6F4UJbIYCTnIWIevJa73UjIFyTuYvjfU5JPEDUUUU X-Originating-IP: [221.216.140.210] X-CM-SenderInfo: pvl13qplvuuh5lvft2wodfhubq/1tbiCwkLClz4kjGDwwAAsE X-Spam-Status: No, score=-8.4 required=5.0 tests=BAYES_00, FORGED_SPF_HELO, GIT_PATCH_0, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, RCVD_IN_BARRACUDACENTRAL, SPF_HELO_PASS, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ben.marshall@pqshield.com, cmuellner@ventanamicro.com, andrew@sifive.com, Richard.Newell@microchip.com, jiawei@iscas.ac.cn, mjos@pqshield.com, kito.cheng@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: SiYu Wu --- gcc/common/config/riscv/riscv-common.c | 2 ++ gcc/config/riscv/crypto.md | 21 +++++++++++++++++++++ gcc/config/riscv/riscv-opts.h | 2 ++ 3 files changed, 25 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index c0432c93dd3..d4d61bd765d 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -109,6 +109,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zkne", ISA_SPEC_CLASS_NONE, 1, 0}, {"zknd", ISA_SPEC_CLASS_NONE, 1, 0}, {"zknh", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zksed", ISA_SPEC_CLASS_NONE, 1, 0}, /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} @@ -923,6 +924,7 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zknd", &gcc_options::x_riscv_zk_subext, MASK_ZKND}, {"zkne", &gcc_options::x_riscv_zk_subext, MASK_ZKNE}, {"zknh", &gcc_options::x_riscv_zk_subext, MASK_ZKNH}, + {"zksed", &gcc_options::x_riscv_zk_subext, MASK_ZKSED}, {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/crypto.md b/gcc/config/riscv/crypto.md index 243a77ef528..ac0107f43c2 100644 --- a/gcc/config/riscv/crypto.md +++ b/gcc/config/riscv/crypto.md @@ -38,6 +38,8 @@ (define_c_enum "unspec" [ UNSPEC_SHA_512_SIG1_2 UNSPEC_SHA_512_SUM0 UNSPEC_SHA_512_SUM1 + UNSPEC_SM4_ED + UNSPEC_SM4_KS ]) @@ -250,3 +252,22 @@ (define_insn "riscv_sha512sum1" "TARGET_ZKNH && TARGET_64BIT" "sha512sum1\t%0,%1") + +;; Zksed - SM4 + +(define_insn "riscv_sm4ed_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "")] + UNSPEC_SM4_ED))] + "TARGET_ZKSED" + "sm4ed\t%0,%1,%2") + +(define_insn "riscv_sm4ks_" + [(set (match_operand:X 0 "register_operand" "=r") + (unspec:X [(match_operand:X 1 "register_operand" "r") + (match_operand:SI 2 "immediate_operand" "")] + UNSPEC_SM4_KS))] + "TARGET_ZKSED" + "sm4ks\t%0,%1,%2") + diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 9d8e560c4ba..6ad89db42f5 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -86,9 +86,11 @@ enum stack_protector_guard { #define MASK_ZKNE (1 << 5) #define MASK_ZKND (1 << 6) #define MASK_ZKNH (1 << 7) +#define MASK_ZKSED (1 << 9) #define TARGET_ZKNE ((riscv_zk_subext & MASK_ZKNE) != 0) #define TARGET_ZKND ((riscv_zk_subext & MASK_ZKND) != 0) #define TARGET_ZKNH ((riscv_zk_subext & MASK_ZKNH) != 0) +#define TARGET_ZKSED ((riscv_zk_subext & MASK_ZKSED) != 0) #endif /* ! GCC_RISCV_OPTS_H */