From patchwork Thu Oct 28 13:52:44 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jiawei X-Patchwork-Id: 46750 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 363843857811 for ; Thu, 28 Oct 2021 13:56:38 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from cstnet.cn (smtp25.cstnet.cn [159.226.251.25]) by sourceware.org (Postfix) with ESMTP id 315C53857827 for ; Thu, 28 Oct 2021 13:53:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 315C53857827 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=iscas.ac.cn Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=iscas.ac.cn Received: from localhost.localdomain (unknown [47.106.84.205]) by APP-05 (Coremail) with SMTP id zQCowAB3f6tGq3phNISDBQ--.2609S3; Thu, 28 Oct 2021 21:53:22 +0800 (CST) From: jiawei To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/3] RISC-V: Minimal support of zfinx extension Date: Thu, 28 Oct 2021 21:52:44 +0800 Message-Id: <20211028135246.9699-2-jiawei@iscas.ac.cn> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20211028135246.9699-1-jiawei@iscas.ac.cn> References: <20211028135246.9699-1-jiawei@iscas.ac.cn> MIME-Version: 1.0 X-CM-TRANSID: zQCowAB3f6tGq3phNISDBQ--.2609S3 X-Coremail-Antispam: 1UD129KBjvJXoW7tF43Xr1xXr43Aw1fWFW5trb_yoW8tryfpa 95Gw43A34FqFsrWa1xtrW8W345Jwn3Kr1rAa1ku34UAayDXrW8AFn0934avrWkXFWYvr92 y3WFk3yYvw4UG37anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUPq14x267AKxVW5JVWrJwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2048vs2IY020E87I2jVAFwI0_Jr4l82xGYIkIc2 x26xkF7I0E14v26r1I6r4UM28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48ve4kI8wA2z4x0 Y4vE2Ix0cI8IcVAFwI0_Jr0_JF4l84ACjcxK6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l84 ACjcxK6I8E87Iv67AKxVWxJr0_GcWl84ACjcxK6I8E87Iv6xkF7I0E14v26rxl6s0DM2AI xVAIcxkEcVAq07x20xvEncxIr21l5I8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20x vE14v26r1j6r18McIj6I8E87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xv r2IYc2Ij64vIr41lF7I21c0EjII2zVCS5cI20VAGYxC7M4IIrI8v6xkF7I0E8cxan2IY04 v7MxkIecxEwVAFjwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s02 6c02F40E14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw 0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6r4j6FyUMIIF0xvEx4A2jsIE14 v26r1j6r4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x 0pRXdbnUUUUU= X-Originating-IP: [47.106.84.205] X-CM-SenderInfo: 5mld4v3l6l2u1dvotugofq/1tbiCwcIAFz4kioKZAAAs2 X-Spam-Status: No, score=-11.1 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, andrew@sifive.com, sinan , tariq.kurd=huawei.com@lists.riscv.org, jiawei , kito.cheng@sifive.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Co-Authored-By: sinan --- gcc/common/config/riscv/riscv-common.c | 6 ++++++ gcc/config/riscv/riscv-opts.h | 6 ++++++ gcc/config/riscv/riscv.opt | 3 +++ 3 files changed, 15 insertions(+) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 37b6ea80086..ab48909e338 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -106,6 +106,9 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zbc", ISA_SPEC_CLASS_NONE, 1, 0}, {"zbs", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zfinx", ISA_SPEC_CLASS_NONE, 1, 0}, + {"zdinx", ISA_SPEC_CLASS_NONE, 1, 0}, + /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -916,6 +919,9 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zbc", &gcc_options::x_riscv_zb_subext, MASK_ZBC}, {"zbs", &gcc_options::x_riscv_zb_subext, MASK_ZBS}, + {"zfinx", &gcc_options::x_riscv_zf_subext, MASK_ZFINX}, + {"zdinx", &gcc_options::x_riscv_zf_subext, MASK_ZDINX}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index 2efc4b80f1f..5a790a028cf 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -83,4 +83,10 @@ enum stack_protector_guard { #define TARGET_ZBC ((riscv_zb_subext & MASK_ZBC) != 0) #define TARGET_ZBS ((riscv_zb_subext & MASK_ZBS) != 0) +#define MASK_ZFINX (1 << 0) +#define MASK_ZDINX (1 << 1) + +#define TARGET_ZFINX ((riscv_zf_subext & MASK_ZFINX) != 0) +#define TARGET_ZDINX ((riscv_zf_subext & MASK_ZDINX) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index 15bf89e17c2..54d27747eff 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -198,6 +198,9 @@ int riscv_zi_subext TargetVariable int riscv_zb_subext +TargetVariable +int riscv_zf_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):