diff mbox series

[committed] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern

Message ID 20211028065501.5373-1-kito.cheng@sifive.com
State Committed
Commit 2dc835cd0b5183a0e30b2b052362ad05f5c082b0
Headers
Series [committed] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern |

Commit Message

Kito Cheng Oct. 28, 2021, 6:55 a.m. UTC 
  We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
only ZBA provide zero_extendsidi2 instruction.

gcc/ChangeLog

	* config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
	use this pattern.
---
 gcc/config/riscv/riscv.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f2..225e5b259c1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1311,7 +1311,7 @@  (define_insn_and_split "*zero_extendsidi2_internal"
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
+  "TARGET_64BIT && !TARGET_ZBA"
   "@
    #
    lwu\t%0,%1"