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Wed, 27 Oct 2021 10:51:26 +0800 (CST) From: shihua@iscas.ac.cn To: gcc-patches@gcc.gnu.org Subject: RISCV: Add zmmul extension Date: Wed, 27 Oct 2021 10:51:16 +0800 Message-Id: <20211027025116.1720-1-shihua@iscas.ac.cn> X-Mailer: git-send-email 2.31.1.windows.1 MIME-Version: 1.0 X-CM-TRANSID: zQCowADHqO2svnhhogtVBQ--.27783S2 X-Coremail-Antispam: 1UD129KBjvJXoWxKry8Xw13Kr1xKr4UWw1kuFg_yoWfXFy8pF WDGw4jkryrXr4Sgws5KFW8Xw1UAF12gr4jvFn8urWqyw18W397t3ZYk3sFyay7XF4YvrW7 CF10kw13u3y5Cw7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUU9014x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2Wl Yx0E2Ix0cI8IcVAFwI0_Jr0_Jr4lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbV WUJVW8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7Cj xVA2Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxAIw28IcxkI7VAKI48JMxC20s026xCaFVCjc4 AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_Jr0_Jr4lx2IqxVCjr7xvwVAFwI0_JrI_JrWlx4CE 17CEb7AF67AKxVWUtVW8ZwCIc40Y0x0EwIxGrwCI42IY6xIIjxv20xvE14v26r1j6r1xMI IF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20EY4v20xvaj40_WFyUJVCq 3wCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I0E14v26r1j6r4UYxBIda VFxhVjvjDU0xZFpf9x0JUm2NtUUUUU= X-Originating-IP: [180.111.126.152] X-CM-SenderInfo: xvklx33d6l2u1dvotugofq/1tbiCwoHEVz4kiSmJgAAsF X-Spam-Status: No, score=-13.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, SPF_HELO_PASS, SPF_PASS autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: cmuellner@ventanamicro.com, andrew@sifive.com, jiawei@iscas.ac.cn, anku.anand@gmail.com, kito.cheng@sifive.com, Liaoshihua Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Liaoshihua --- gcc/common/config/riscv/riscv-common.c | 3 +++ gcc/config/riscv/riscv-c.c | 2 +- gcc/config/riscv/riscv-opts.h | 3 +++ gcc/config/riscv/riscv.c | 5 ++++- gcc/config/riscv/riscv.md | 30 +++++++++++++------------- gcc/config/riscv/riscv.opt | 3 +++ 6 files changed, 29 insertions(+), 17 deletions(-) diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c index 34b74e52a2d..ad3180677be 100644 --- a/gcc/common/config/riscv/riscv-common.c +++ b/gcc/common/config/riscv/riscv-common.c @@ -101,6 +101,7 @@ static const struct riscv_ext_version riscv_ext_version_table[] = {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0}, {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0}, + {"zmmul", ISA_SPEC_CLASS_NONE, 0, 1}, /* Terminate the list. */ {NULL, ISA_SPEC_CLASS_NONE, 0, 0} }; @@ -904,6 +905,8 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] = {"zicsr", &gcc_options::x_riscv_zi_subext, MASK_ZICSR}, {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI}, + {"zmmul", &gcc_options::x_riscv_zmmul_subext, MASK_ZMMUL}, + {NULL, NULL, 0} }; diff --git a/gcc/config/riscv/riscv-c.c b/gcc/config/riscv/riscv-c.c index efd4a61ea29..72aa4e389c0 100644 --- a/gcc/config/riscv/riscv-c.c +++ b/gcc/config/riscv/riscv-c.c @@ -47,7 +47,7 @@ riscv_cpu_cpp_builtins (cpp_reader *pfile) if (TARGET_ATOMIC) builtin_define ("__riscv_atomic"); - if (TARGET_MUL) + if (TARGET_MUL || TARGET_ZMMUL) builtin_define ("__riscv_mul"); if (TARGET_DIV) builtin_define ("__riscv_div"); diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h index f4cf6ca4b82..c52b18ebd80 100644 --- a/gcc/config/riscv/riscv-opts.h +++ b/gcc/config/riscv/riscv-opts.h @@ -73,4 +73,7 @@ enum stack_protector_guard { #define TARGET_ZICSR ((riscv_zi_subext & MASK_ZICSR) != 0) #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0) +#define MASK_ZMMUL (1 << 0) +#define TARGET_ZMMUL ((riscv_zmmul_subext & MASK_ZMMUL) != 0) + #endif /* ! GCC_RISCV_OPTS_H */ diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 17cdf705c32..4f5cb35e625 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -1872,7 +1872,7 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN case MULT: if (float_mode_p) *total = tune_param->fp_mul[mode == DFmode]; - else if (!TARGET_MUL) + else if (!TARGET_MUL && !TARGET_ZMMUL) /* Estimate the cost of a library call. */ *total = COSTS_N_INSNS (speed ? 32 : 6); else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) @@ -4736,6 +4736,9 @@ riscv_option_override (void) if (flag_pic) g_switch_value = 0; + /* zmmul */ + if (TARGET_ZMMUL && TARGET_MUL) + error ("can not use both the % and the % extension"); /* The presence of the M extension implies that division instructions are present, so include them unless explicitly disabled. */ if (TARGET_MUL && (target_flags_explicit & MASK_DIV) == 0) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index c3687d57047..2ee7d801f1a 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -600,7 +600,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] - "TARGET_MUL" + "(TARGET_MUL || TARGET_ZMMUL)" { return TARGET_64BIT ? "mulw\t%0,%1,%2" : "mul\t%0,%1,%2"; } [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -609,7 +609,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" "mul\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -619,7 +619,7 @@ (sign_extend:DI (mult:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -630,7 +630,7 @@ (match_operator:SI 3 "subreg_lowpart_operator" [(mult:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r"))])))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" "mulw\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -648,7 +648,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (any_extend:TI (match_operand:DI 1 "register_operand")) (any_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -670,7 +670,7 @@ (any_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -679,7 +679,7 @@ [(set (match_operand:TI 0 "register_operand") (mult:TI (zero_extend:TI (match_operand:DI 1 "register_operand")) (sign_extend:TI (match_operand:DI 2 "register_operand"))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" { rtx low = gen_reg_rtx (DImode); emit_insn (gen_muldi3 (low, operands[1], operands[2])); @@ -701,7 +701,7 @@ (sign_extend:TI (match_operand:DI 2 "register_operand" " r"))) (const_int 64))))] - "TARGET_MUL && TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "DI")]) @@ -712,7 +712,7 @@ (match_operand:SI 1 "register_operand" " r")) (any_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -731,7 +731,7 @@ (any_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && !TARGET_64BIT" "mulh\t%0,%1,%2" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -743,7 +743,7 @@ (match_operand:SI 1 "register_operand" " r")) (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && !TARGET_64BIT" { rtx temp = gen_reg_rtx (SImode); emit_insn (gen_mulsi3 (temp, operands[1], operands[2])); @@ -762,7 +762,7 @@ (sign_extend:DI (match_operand:SI 2 "register_operand" " r"))) (const_int 32))))] - "TARGET_MUL && !TARGET_64BIT" + "(TARGET_MUL || TARGET_ZMMUL) && !TARGET_64BIT" "mulhsu\t%0,%2,%1" [(set_attr "type" "imul") (set_attr "mode" "SI")]) @@ -779,7 +779,7 @@ [(set (match_operand:SI 0 "register_operand" "=r") (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r")))] - "TARGET_DIV" + "!TARGET_ZMMUL && TARGET_DIV" { return TARGET_64BIT ? "%i2w\t%0,%1,%2" : "%i2\t%0,%1,%2"; } [(set_attr "type" "idiv") (set_attr "mode" "SI")]) @@ -788,7 +788,7 @@ [(set (match_operand:DI 0 "register_operand" "=r") (any_div:DI (match_operand:DI 1 "register_operand" " r") (match_operand:DI 2 "register_operand" " r")))] - "TARGET_DIV && TARGET_64BIT" + "!TARGET_ZMMUL && TARGET_DIV && TARGET_64BIT" "%i2\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI")]) @@ -798,7 +798,7 @@ (sign_extend:DI (any_div:SI (match_operand:SI 1 "register_operand" " r") (match_operand:SI 2 "register_operand" " r"))))] - "TARGET_DIV && TARGET_64BIT" + "!TARGET_ZMMUL && TARGET_DIV && TARGET_64BIT" "%i2w\t%0,%1,%2" [(set_attr "type" "idiv") (set_attr "mode" "DI")]) diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt index e294e223151..f7ccfcee41d 100644 --- a/gcc/config/riscv/riscv.opt +++ b/gcc/config/riscv/riscv.opt @@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0 TargetVariable int riscv_zi_subext +TargetVariable +int riscv_zmmul_subext + Enum Name(isa_spec_class) Type(enum riscv_isa_spec_class) Supported ISA specs (for use with the -misa-spec= option):