diff mbox series

AVX512FP16: Fix ICE for 2 v4hf vector concat

Message ID 20211015050603.59842-1-hongyu.wang@intel.com
State Committed
Commit 575191b976a5175be6579590b05f1f1d3550cefc
Headers show
Series AVX512FP16: Fix ICE for 2 v4hf vector concat | expand

Commit Message

Hongyu Wang Oct. 15, 2021, 5:06 a.m. UTC
Hi,

For V4HFmode, doing vector concat like

__builtin_shufflevector (a, b, {0, 1, 2, 3, 4, 5, 6, 7})

could trigger ICE since it is not handled in ix86_vector_init ().

Handle HFmode like HImode to avoid such ICE.

Bootstrappted/regtested on x86_64-pc-linux-gnu{-m32,} and sde{-m32,}

OK for master?

gcc/ChangeLog:

	* config/i386/i386-expand.c (ix86_expand_vector_init):
	For half_vector concat for HFmode, handle them like HImode.

gcc/testsuite/ChangeLog:

	* gcc.target/i386/avx512fp16-v4hf-concat.c: New test.
---
 gcc/config/i386/i386-expand.c                    |  3 ++-
 .../gcc.target/i386/avx512fp16-v4hf-concat.c     | 16 ++++++++++++++++
 2 files changed, 18 insertions(+), 1 deletion(-)
 create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c

Comments

Hongtao Liu Oct. 15, 2021, 5:34 a.m. UTC | #1
On Fri, Oct 15, 2021 at 1:07 PM Hongyu Wang via Gcc-patches
<gcc-patches@gcc.gnu.org> wrote:
>
> Hi,
>
> For V4HFmode, doing vector concat like
>
> __builtin_shufflevector (a, b, {0, 1, 2, 3, 4, 5, 6, 7})
>
> could trigger ICE since it is not handled in ix86_vector_init ().
>
> Handle HFmode like HImode to avoid such ICE.
>
> Bootstrappted/regtested on x86_64-pc-linux-gnu{-m32,} and sde{-m32,}
>
> OK for master?
>
Ok.
> gcc/ChangeLog:
>
>         * config/i386/i386-expand.c (ix86_expand_vector_init):
>         For half_vector concat for HFmode, handle them like HImode.
>
> gcc/testsuite/ChangeLog:
>
>         * gcc.target/i386/avx512fp16-v4hf-concat.c: New test.
> ---
>  gcc/config/i386/i386-expand.c                    |  3 ++-
>  .../gcc.target/i386/avx512fp16-v4hf-concat.c     | 16 ++++++++++++++++
>  2 files changed, 18 insertions(+), 1 deletion(-)
>  create mode 100644 gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c
>
> diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
> index 95274201f4f..1b011047251 100644
> --- a/gcc/config/i386/i386-expand.c
> +++ b/gcc/config/i386/i386-expand.c
> @@ -15122,7 +15122,8 @@ ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
>           rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) };
>           if (inner_mode == QImode
>               || inner_mode == HImode
> -             || inner_mode == TImode)
> +             || inner_mode == TImode
> +             || inner_mode == HFmode)
>             {
>               unsigned int n_bits = n_elts * GET_MODE_SIZE (inner_mode);
>               scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode;
> diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c
> new file mode 100644
> index 00000000000..3b8a7f39b85
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c
> @@ -0,0 +1,16 @@
> +/* { dg-do compile } */
> +/* { dg-options "-mavx512fp16 -O2" } */
> +/* { dg-final { scan-assembler-times "vpunpcklqdq" 1 } } */
> +
> +typedef _Float16 v8hf __attribute__((vector_size (16)));
> +typedef _Float16 v4hf __attribute__((vector_size (8)));
> +
> +v8hf foov (v4hf a, v4hf b)
> +{
> +    return __builtin_shufflevector (a, b, 0, 1, 2, 3, 4, 5, 6, 7);
> +}
> +
> +v8hf foov2 (v4hf a)
> +{
> +    return __builtin_shufflevector (a, (v4hf){0}, 0, 1, 2, 3, 4, 5, 6, 7);
> +}
> --
> 2.27.1
>
diff mbox series

Patch

diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c
index 95274201f4f..1b011047251 100644
--- a/gcc/config/i386/i386-expand.c
+++ b/gcc/config/i386/i386-expand.c
@@ -15122,7 +15122,8 @@  ix86_expand_vector_init (bool mmx_ok, rtx target, rtx vals)
 	  rtx ops[2] = { XVECEXP (vals, 0, 0), XVECEXP (vals, 0, 1) };
 	  if (inner_mode == QImode
 	      || inner_mode == HImode
-	      || inner_mode == TImode)
+	      || inner_mode == TImode
+	      || inner_mode == HFmode)
 	    {
 	      unsigned int n_bits = n_elts * GET_MODE_SIZE (inner_mode);
 	      scalar_mode elt_mode = inner_mode == TImode ? DImode : SImode;
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c
new file mode 100644
index 00000000000..3b8a7f39b85
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-v4hf-concat.c
@@ -0,0 +1,16 @@ 
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vpunpcklqdq" 1 } } */
+
+typedef _Float16 v8hf __attribute__((vector_size (16)));
+typedef _Float16 v4hf __attribute__((vector_size (8)));
+
+v8hf foov (v4hf a, v4hf b)
+{
+    return __builtin_shufflevector (a, b, 0, 1, 2, 3, 4, 5, 6, 7);
+}
+
+v8hf foov2 (v4hf a)
+{
+    return __builtin_shufflevector (a, (v4hf){0}, 0, 1, 2, 3, 4, 5, 6, 7);
+}