[v2,03/14] arm: Add tests for PR target/101325
Commit Message
These tests are derived from the one provided in the PR: there is a
compile-only test because I did not have access to anything that could
execute MVE code until recently.
I have been able to add an executable test since QEMU supports MVE.
Instead of adding arm_v8_1m_mve_hw, I update arm_mve_hw so that it
uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does. This
ensures arm_mve_hw passes even if the toolchain does not generate MVE
code by default.
2021-10-13 Christophe Lyon <christophe.lyon@foss.st.com>
gcc/testsuite/
PR target/101325
* gcc.target/arm/simd/pr101325.c: New.
* gcc.target/arm/simd/pr101325-2.c: New.
* lib/target-supports.exp (check_effective_target_arm_mve_hw): Use
add_options_for_arm_v8_1m_mve_fp.
add executable test and update check_effective_target_arm_mve_hw
Comments
Christophe Lyon via Gcc-patches <gcc-patches@gcc.gnu.org> writes:
> These tests are derived from the one provided in the PR: there is a
> compile-only test because I did not have access to anything that could
> execute MVE code until recently.
> I have been able to add an executable test since QEMU supports MVE.
>
> Instead of adding arm_v8_1m_mve_hw, I update arm_mve_hw so that it
> uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does. This
> ensures arm_mve_hw passes even if the toolchain does not generate MVE
> code by default.
>
> 2021-10-13 Christophe Lyon <christophe.lyon@foss.st.com>
>
> gcc/testsuite/
> PR target/101325
> * gcc.target/arm/simd/pr101325.c: New.
> * gcc.target/arm/simd/pr101325-2.c: New.
> * lib/target-supports.exp (check_effective_target_arm_mve_hw): Use
> add_options_for_arm_v8_1m_mve_fp.
>
> add executable test and update check_effective_target_arm_mve_hw
>
> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c b/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c
> new file mode 100644
> index 00000000000..7907a386385
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c
> @@ -0,0 +1,19 @@
> +/* { dg-do run } */
> +/* { dg-require-effective-target arm_mve_hw } */
> +/* { dg-options "-O3" } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +
> +#include <arm_mve.h>
> +
> +
> +__attribute((noinline,noipa))
Very minor, but: noinline is redundant with noipa.
Richard
> +unsigned foo(int8x16_t v, int8x16_t w)
> +{
> + return vcmpeqq (v, w);
> +}
> +
> +int main(void)
> +{
> + if (foo (vdupq_n_s8(0), vdupq_n_s8(0)) != 0xffffU)
> + __builtin_abort ();
> +}
> diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
> new file mode 100644
> index 00000000000..a466683a0b1
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/arm/simd/pr101325.c
> @@ -0,0 +1,14 @@
> +/* { dg-do compile } */
> +/* { dg-require-effective-target arm_v8_1m_mve_ok } */
> +/* { dg-add-options arm_v8_1m_mve } */
> +/* { dg-additional-options "-O3" } */
> +
> +#include <arm_mve.h>
> +
> +unsigned foo(int8x16_t v, int8x16_t w)
> +{
> + return vcmpeqq (v, w);
> +}
> +/* { dg-final { scan-assembler {\tvcmp.i8 eq} } } */
> +/* { dg-final { scan-assembler {\tvmrs\t r[0-9]+, P0} } } */
> +/* { dg-final { scan-assembler {\tuxth} } } */
> diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp
> index e030e4f376b..b0e35b602af 100644
> --- a/gcc/testsuite/lib/target-supports.exp
> +++ b/gcc/testsuite/lib/target-supports.exp
> @@ -4889,6 +4889,7 @@ proc check_effective_target_arm_cmse_hw { } {
> }
> } "-mcmse -Wl,--section-start,.gnu.sgstubs=0x00400000"]
> }
> +
> # Return 1 if the target supports executing MVE instructions, 0
> # otherwise.
>
> @@ -4904,7 +4905,7 @@ proc check_effective_target_arm_mve_hw {} {
> : "0" (a), "r" (b));
> return (a != 2);
> }
> - } ""]
> + } [add_options_for_arm_v8_1m_mve_fp ""]]
> }
>
> # Return 1 if this is an ARM target where ARMv8-M Security Extensions with
new file mode 100644
@@ -0,0 +1,19 @@
+/* { dg-do run } */
+/* { dg-require-effective-target arm_mve_hw } */
+/* { dg-options "-O3" } */
+/* { dg-add-options arm_v8_1m_mve } */
+
+#include <arm_mve.h>
+
+
+__attribute((noinline,noipa))
+unsigned foo(int8x16_t v, int8x16_t w)
+{
+ return vcmpeqq (v, w);
+}
+
+int main(void)
+{
+ if (foo (vdupq_n_s8(0), vdupq_n_s8(0)) != 0xffffU)
+ __builtin_abort ();
+}
new file mode 100644
@@ -0,0 +1,14 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_v8_1m_mve_ok } */
+/* { dg-add-options arm_v8_1m_mve } */
+/* { dg-additional-options "-O3" } */
+
+#include <arm_mve.h>
+
+unsigned foo(int8x16_t v, int8x16_t w)
+{
+ return vcmpeqq (v, w);
+}
+/* { dg-final { scan-assembler {\tvcmp.i8 eq} } } */
+/* { dg-final { scan-assembler {\tvmrs\t r[0-9]+, P0} } } */
+/* { dg-final { scan-assembler {\tuxth} } } */
@@ -4889,6 +4889,7 @@ proc check_effective_target_arm_cmse_hw { } {
}
} "-mcmse -Wl,--section-start,.gnu.sgstubs=0x00400000"]
}
+
# Return 1 if the target supports executing MVE instructions, 0
# otherwise.
@@ -4904,7 +4905,7 @@ proc check_effective_target_arm_mve_hw {} {
: "0" (a), "r" (b));
return (a != 2);
}
- } ""]
+ } [add_options_for_arm_v8_1m_mve_fp ""]]
}
# Return 1 if this is an ARM target where ARMv8-M Security Extensions with