From patchwork Tue Sep 28 06:42:16 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: liuhongt X-Patchwork-Id: 45488 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id BC85B3858414 for ; Tue, 28 Sep 2021 06:42:51 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BC85B3858414 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gcc.gnu.org; s=default; t=1632811371; bh=tSPNxMibqO3NiK+SlLmK6uQ21oOCodhlw6tfiUkbJxM=; h=To:Subject:Date:List-Id:List-Unsubscribe:List-Archive:List-Post: List-Help:List-Subscribe:From:Reply-To:From; b=gRdfuj/f66B6G8q+RHs7SRYuP9FUfWXd0XM41la6W2a0AFyzMalTYe1mM3wpgQsxU oBvy5BSzGlbIqpJuOvmrLBqfBqUPyRBKmM1maE4kt02tNUDTQ9QtL5Az/FAc685BI+ NHx5igmt/dC5i9hundTs/jjFKt3O06i3atV5fCZM= X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by sourceware.org (Postfix) with ESMTPS id 41FAC3858409 for ; Tue, 28 Sep 2021 06:42:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 41FAC3858409 X-IronPort-AV: E=McAfee;i="6200,9189,10120"; a="211714628" X-IronPort-AV: E=Sophos;i="5.85,328,1624345200"; d="scan'208";a="211714628" Received: from fmsmga002.fm.intel.com ([10.253.24.26]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Sep 2021 23:42:19 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.85,328,1624345200"; d="scan'208";a="561835413" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga002.fm.intel.com with ESMTP; 27 Sep 2021 23:42:18 -0700 Received: from shliclel219.sh.intel.com (shliclel219.sh.intel.com [10.239.236.219]) by scymds01.sc.intel.com with ESMTP id 18S6gG3v010492; Mon, 27 Sep 2021 23:42:17 -0700 To: gcc-patches@gcc.gnu.org Subject: [PATCH] [i386] Support reduc_{plus,smax,smin,umax,min}_scal_v4hi. Date: Tue, 28 Sep 2021 14:42:16 +0800 Message-Id: <20210928064216.901551-1-hongtao.liu@intel.com> X-Mailer: git-send-email 2.27.0 MIME-Version: 1.0 X-Spam-Status: No, score=-11.6 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_NONE, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_SHORT, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: liuhongt via Gcc-patches From: liuhongt Reply-To: liuhongt Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi: Bootstrapped and regtested on x86_64-pc-lunux-gnu{-m32,}. Ok for trunk? gcc/ChangeLog: PR target/102494 * config/i386/i386-expand.c (emit_reduc_half): Hanlde V4HImode. * config/i386/mmx.md (reduc_plus_scal_v4hi): New. (reduc__scal_v4hi): New. gcc/testsuite/ChangeLog: * gcc.target/i386/mmx-reduce-op-1.c: New test. * gcc.target/i386/mmx-reduce-op-2.c: New test. --- gcc/config/i386/i386-expand.c | 5 ++ gcc/config/i386/mmx.md | 36 ++++++++++++ .../gcc.target/i386/mmx-reduce-op-1.c | 58 +++++++++++++++++++ .../gcc.target/i386/mmx-reduce-op-2.c | 25 ++++++++ 4 files changed, 124 insertions(+) create mode 100644 gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c create mode 100644 gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 94ac303585e..260e7fd32a8 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -16043,6 +16043,11 @@ emit_reduc_half (rtx dest, rtx src, int i) case E_V2DFmode: tem = gen_vec_interleave_highv2df (dest, src, src); break; + case E_V4HImode: + d = gen_reg_rtx (V1DImode); + tem = gen_mmx_lshrv1di3 (d, gen_lowpart (V1DImode, src), + GEN_INT (i / 2)); + break; case E_V16QImode: case E_V8HImode: case E_V4SImode: diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index b0093778fc6..126a2dd4b7e 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -3931,6 +3931,42 @@ (define_expand "reduc_plus_scal_v8qi" DONE; }) +(define_expand "reduc_plus_scal_v4hi" + [(plus:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_addv4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + +(define_expand "reduc__scal_v4hi" + [(smaxmin:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_v4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + +(define_expand "reduc__scal_v4hi" + [(umaxmin:V4HI + (match_operand:HI 0 "register_operand") + (match_operand:V4HI 1 "register_operand"))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" +{ + rtx tmp = gen_reg_rtx (V4HImode); + ix86_expand_reduc (gen_v4hi3, tmp, operands[1]); + emit_insn (gen_vec_extractv4hihi (operands[0], tmp, const0_rtx)); + DONE; +}) + (define_expand "usadv8qi" [(match_operand:V2SI 0 "register_operand") (match_operand:V8QI 1 "register_operand") diff --git a/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c new file mode 100644 index 00000000000..ac20ed0d41f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-1.c @@ -0,0 +1,58 @@ +/* { dg-do compile { target { ! ia32 } } } */ +/* { dg-options "-O2 -fdump-tree-optimized" } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_PLUS" 1 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_MIN" 2 "optimized" } } */ +/* { dg-final { scan-tree-dump-times "\.REDUC_MAX" 2 "optimized" } } */ + +#define MAX(a, b) ((a) > (b) ? (a) : (b)) +#define MIN(a, b) ((a) > (b) ? (b) : (a)) + +short +__attribute__((noipa, optimize("Ofast"),target("sse2"))) +reduce_add (short* __restrict pa) +{ + short sum = 0; + for (int i = 0; i != 4; i++) + sum += pa[i]; + return sum; +} + +short +__attribute__((noipa, optimize("Ofast"),target("sse2"))) +reduce_smax (short* __restrict pa) +{ + short sum = pa[0]; + for (int i = 0; i != 4; i++) + sum = MAX(sum, pa[i]); + return sum; +} + +short +__attribute__((noipa, optimize("Ofast"),target("sse2"))) +reduce_smin (short* __restrict pa) +{ + short sum = pa[0]; + for (int i = 0; i != 4; i++) + sum = MIN(sum, pa[i]); + return sum; +} + +unsigned short +__attribute__((noipa, optimize("Ofast"),target("sse4.1"))) +reduce_umax (unsigned short* __restrict pa) +{ + unsigned short sum = pa[0]; + for (int i = 0; i != 4; i++) + sum = MAX(sum, pa[i]); + return sum; +} + +unsigned short +__attribute__((noipa, optimize("Ofast"),target("sse4.1"))) +reduce_umin (unsigned short* __restrict pa) +{ + unsigned short sum = pa[0]; + for (int i = 0; i != 4; i++) + sum = MIN(sum, pa[i]); + return sum; +} diff --git a/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c new file mode 100644 index 00000000000..0896cd6d9be --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/mmx-reduce-op-2.c @@ -0,0 +1,25 @@ +/* { dg-do run { target { ! ia32 } } } */ +/* { dg-require-effective-target sse4 } */ +/* { dg-options "-O2 -msse4.1" } */ + +#include "sse4_1-check.h" + +#include "mmx-reduce-op-1.c" + +static void +sse4_1_test () +{ + short p[4] = { -103, 23, 41, 200 }; + unsigned short up[4] = { 100, 30, 299, 1000 }; + + if (reduce_add (p) != 161) + abort (); + if (reduce_smin (p) != -103) + abort (); + if (reduce_smax (p) != 200) + abort (); + if (reduce_umin (up) != 30) + abort (); + if (reduce_umax (up) != 1000) + abort(); +}