diff mbox series

[RFC,8/8] RISC-V: Cost model for ZBS extension.

Message ID 20210923075731.50125-9-kito.cheng@sifive.com
State Committed
Commit 77b84fb0a8eac736f456e42b6a7801a76e4644eb
Headers show
Series RISC-V: Bit-manipulation extension. | expand

Commit Message

Kito Cheng Sept. 23, 2021, 7:57 a.m. UTC
2021-09-23 Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_rtx_costs): Handle cost model
	for zbs extension.
---
 gcc/config/riscv/riscv.c | 47 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index 77981d8e818..055111ac30c 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1851,6 +1851,24 @@  riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	    *total = COSTS_N_INSNS (1);
 	    return true;
 	}
+      /* bclri pattern for zbs.  */
+      if (TARGET_ZBS
+	  && not_single_bit_mask_operand (XEXP (x, 1), VOIDmode))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      /* bclr pattern for zbs.  */
+      if (TARGET_ZBS
+	  && REG_P (XEXP (x, 1))
+	  && GET_CODE (XEXP (x, 0)) == ROTATE
+	  && CONST_INT_P (XEXP ((XEXP (x, 0)), 0))
+	  && INTVAL (XEXP ((XEXP (x, 0)), 0)) == -2)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+
       gcc_fallthrough ();
     case IOR:
     case XOR:
@@ -1861,6 +1879,18 @@  riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  *total = riscv_binary_cost (x, 1, 2);
 	  return true;
 	}
+
+      /* bset[i] and binv[i] pattern for zbs.  */
+      if ((GET_CODE (x) == IOR || GET_CODE (x) == XOR)
+	  && TARGET_ZBS
+	  && ((GET_CODE (XEXP (x, 0)) == ASHIFT
+	      && CONST_INT_P (XEXP (XEXP (x, 0), 0)))
+	      || single_bit_mask_operand (XEXP (x, 1), VOIDmode)))
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+
       /* Double-word operations use two single-word operations.  */
       *total = riscv_binary_cost (x, 1, 2);
       return false;
@@ -1876,9 +1906,26 @@  riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
 	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
 	  return true;
 	}
+      /* bext pattern for zbs.  */
+      if (TARGET_ZBS && outer_code == SET
+	  && GET_CODE (XEXP (x, 1)) == CONST_INT
+	  && INTVAL (XEXP (x, 1)) == 1)
+	{
+	  *total = COSTS_N_INSNS (SINGLE_SHIFT_COST);
+	  return true;
+	}
       return false;
 
     case ASHIFT:
+      /* bset pattern for zbs.  */
+      if (TARGET_ZBS
+	  && CONST_INT_P (XEXP (x, 0))
+	  && INTVAL (XEXP (x, 0)) == 1)
+	{
+	  *total = COSTS_N_INSNS (1);
+	  return true;
+	}
+      gcc_fallthrough ();
     case ASHIFTRT:
     case LSHIFTRT:
       *total = riscv_binary_cost (x, SINGLE_SHIFT_COST,