From patchwork Thu Sep 23 07:57:29 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 45343 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 279AF3857C4A for ; Thu, 23 Sep 2021 08:01:11 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from mail-pj1-x102a.google.com (mail-pj1-x102a.google.com [IPv6:2607:f8b0:4864:20::102a]) by sourceware.org (Postfix) with ESMTPS id D32A6385842B for ; Thu, 23 Sep 2021 07:57:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org D32A6385842B Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=sifive.com Received: by mail-pj1-x102a.google.com with SMTP id d13-20020a17090ad3cd00b0019e746f7bd4so1128318pjw.0 for ; Thu, 23 Sep 2021 00:57:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=V3tp/YTC6R7YR0cdRuyTa5AYEfzWbZrJ5VV4vDAcwXE=; b=U9X8iArv1qvH9KsohDaD4Eb+uG4VFOpXeTZHebE3vzhIrcx7hG8k4spS5OJy9qsgiC 0SiMReG72zv6tSmp7sh360mJaf9744xToWPPVf8HbJCWC3/W+JrEVn7PkxFR+G2nc0+q /fe5LWNAt6Ck5e1cKuLnx+ZNq593PsmsIi5GBsOZgwLoPA5OZd85Y2yFPkQ55iS/P/iN HoDZOPh432Tz/blahfFwQ+5lnuCGH2s9tXgYAZQYbwIjqy0NEhEIDZZdpX1GWD+jtCmR B7Lm5rkDWJNyXxxeZwEgenSns0B3+l4ZhELQHvUAdDZjb/t1gJC1a609FYefBdk8S2so 6UUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V3tp/YTC6R7YR0cdRuyTa5AYEfzWbZrJ5VV4vDAcwXE=; b=td3D+JN56/D4zI6qwy5tYzn3A/F/JkUq4a2O6HWrkazg1PSvHlnDcNkVcWO73LGHE0 4Yo6WXBFbSgf469zaXtC3g8gvRim+PdDh/3r7hnILryeResemM445sKoD3Pkz+sU9xMn 0eoixV9gKEIL0bQL2ERq6jouLEwdopCXx+5ucrfyXXdBy0oDTGuf9htEJRiiUF007TK4 qxmI62Q4Ii+jEtXpintVPH/wNH8NBxTNGCTHtUzKKiLrqBU9EhgdJBQ4jtIN3zTDVQnw hJii9ErJFWocdExizMlmJ0o5s3ABGc9KKBW1FIt01V74sOvdk4b/KYITmlL1XX+at8JP pE3w== X-Gm-Message-State: AOAM532Sc8S3a6QIfgv0r+4o41aw5tmFjptefkvoKBtqzjBKLOx3gxhy 7lxwzNNMJo/gnrs8LkfaUkXJriT2NMDWaQ== X-Google-Smtp-Source: ABdhPJxzhkkY2XgDLmJ692T+T62cuyJNOcSO8roUqenAii91S5lyprtwbbD4P+A2WVjKNDYAaT0d3A== X-Received: by 2002:a17:90b:1c92:: with SMTP id oo18mr16525318pjb.56.1632383869750; Thu, 23 Sep 2021 00:57:49 -0700 (PDT) Received: from hsinchu02.internal.sifive.com (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id pc3sm8132163pjb.0.2021.09.23.00.57.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Sep 2021 00:57:49 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com, jiawei@iscas.ac.cn, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com Subject: [RFC PATCH 6/8] RISC-V: Use li and rori to load constants. Date: Thu, 23 Sep 2021 15:57:29 +0800 Message-Id: <20210923075731.50125-7-kito.cheng@sifive.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923075731.50125-1-kito.cheng@sifive.com> References: <20210923075731.50125-1-kito.cheng@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Jim Wilson gcc/ChangeLog: * config/riscv/riscv.c (riscv_build_integer_1): Build integer with rotate. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-li-rotr.c: New. --- gcc/config/riscv/riscv.c | 41 ++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 +++++++++++++++++ 2 files changed, 76 insertions(+) create mode 100644 gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index 10f7bd21f8d..66daebbbc8f 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -461,6 +461,47 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], } } + if (cost > 2 && TARGET_64BIT && TARGET_ZBB) + { + int leading_ones = clz_hwi (~value); + int trailing_ones = ctz_hwi (~value); + + /* If all bits are one except a few that are zero, and the zero bits + are within a range of 11 bits, and at least one of the upper 32-bits + is a zero, then we can generate a constant by loading a small + negative constant and rotating. */ + if (leading_ones < 32 + && ((64 - leading_ones - trailing_ones) < 12)) + { + codes[0].code = UNKNOWN; + /* The sign-bit might be zero, so just rotate to be safe. */ + codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones) + | (value << (64 - trailing_ones))); + codes[1].code = ROTATERT; + codes[1].value = 64 - trailing_ones; + cost = 2; + } + /* Handle the case where the 11 bit range of zero bits wraps around. */ + else + { + int upper_trailing_ones = ctz_hwi (~value >> 32); + int lower_leading_ones = clz_hwi (~value << 32); + + if (upper_trailing_ones < 32 && lower_leading_ones < 32 + && ((64 - upper_trailing_ones - lower_leading_ones) < 12)) + { + codes[0].code = UNKNOWN; + /* The sign-bit might be zero, so just rotate to be safe. */ + codes[0].value = ((value << (32 - upper_trailing_ones)) + | ((unsigned HOST_WIDE_INT) value + >> (32 + upper_trailing_ones))); + codes[1].code = ROTATERT; + codes[1].value = 32 - upper_trailing_ones; + cost = 2; + } + } + } + gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); return cost; } diff --git a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c new file mode 100644 index 00000000000..03254ed9150 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */ + +long +li_rori (void) +{ + return 0xffff77ffffffffffL; +} + +long +li_rori_2 (void) +{ + return 0x77ffffffffffffffL; +} + +long +li_rori_3 (void) +{ + return 0xfffffffeefffffffL; +} + +long +li_rori_4 (void) +{ + return 0x5ffffffffffffff5L; +} + +long +li_rori_5 (void) +{ + return 0xaffffffffffffffaL; +} + + +/* { dg-final { scan-assembler-times "rori\t" 5 } } */