diff mbox series

[RFC,5/8] RISC-V: Cost model for zbb extension.

Message ID 20210923075731.50125-6-kito.cheng@sifive.com
State Committed
Commit 3329d892eb603fbe4e7c393f19d35739fe400a22
Headers
Series RISC-V: Bit-manipulation extension. |

Commit Message

Kito Cheng Sept. 23, 2021, 7:57 a.m. UTC 
  2021-09-23 Kito Cheng <kito.cheng@sifive.com>

gcc/ChangeLog:

	* config/riscv/riscv.c (riscv_extend_cost): Handle cost model
	for zbb extension.
	(riscv_rtx_costs): Ditto.
---
 gcc/config/riscv/riscv.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)
diff mbox series

Patch

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index cc58b7041ac..10f7bd21f8d 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1706,6 +1706,16 @@  riscv_extend_cost (rtx op, bool unsigned_p)
   if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
     return COSTS_N_INSNS (1);
 
+  /* ZBB provide zext.h, sext.b and sext.h.  */
+  if (TARGET_ZBB)
+    {
+      if (!unsigned_p && GET_MODE (op) == QImode)
+	return COSTS_N_INSNS (1);
+
+      if (GET_MODE (op) == HImode)
+	return COSTS_N_INSNS (1);
+    }
+
   if (!unsigned_p && GET_MODE (op) == SImode)
     /* We can use SEXT.W.  */
     return COSTS_N_INSNS (1);
@@ -1796,6 +1806,13 @@  riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
       gcc_fallthrough ();
     case IOR:
     case XOR:
+      /* orn, andn and xorn pattern for zbb.  */
+      if (TARGET_ZBB
+	  && GET_CODE (XEXP (x, 0)) == NOT)
+	{
+	  *total = riscv_binary_cost (x, 1, 2);
+	  return true;
+	}
       /* Double-word operations use two single-word operations.  */
       *total = riscv_binary_cost (x, 1, 2);
       return false;