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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id pc3sm8132163pjb.0.2021.09.23.00.57.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Sep 2021 00:57:41 -0700 (PDT) From: Kito Cheng To: gcc-patches@gcc.gnu.org, kito.cheng@gmail.com, jimw@sifive.com, jiawei@iscas.ac.cn, cmuellner@ventanamicro.com, palmer@dabbelt.com, andrew@sifive.com Subject: [RFC PATCH 2/8] RISC-V: Implement instruction patterns for ZBA extension. Date: Thu, 23 Sep 2021 15:57:25 +0800 Message-Id: <20210923075731.50125-3-kito.cheng@sifive.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20210923075731.50125-1-kito.cheng@sifive.com> References: <20210923075731.50125-1-kito.cheng@sifive.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.6 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kito Cheng Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" From: Jim Wilson 2021-09-23 Jim Wilson Kito Cheng Jia-Wei Chen gcc/ChangeLog: * config/riscv/bitmanip.md (*zero_extendsidi2_bitmanip): New. (*shNadd): Ditto. (*shNadduw): Ditto. (*add.uw): Ditto. (*slliuw): Ditto. * config/riscv/riscv.c (riscv_extend_cost): Handle cost model for zba extension. (riscv_rtx_costs): Ditto. * config/riscv/riscv.md: Include bitmanip.md (type): Add bitmanip bype. (zero_extendsidi2): Change to define_expand pattern. (*zero_extendsidi2_internal): New. (zero_extendsidi2_shifted): Disable for ZBA. 2021-09-23 Kito Cheng Jia-Wei Chen gcc/testsuite/ChangeLog: * gcc.target/riscv/zba-adduw.c: New. * gcc.target/riscv/zba-shNadd-01.c: Ditto. * gcc.target/riscv/zba-shNadd-02.c: Ditto. * gcc.target/riscv/zba-shNadd-03.c: Ditto. * gcc.target/riscv/zba-slliuw.c: Ditto. * gcc.target/riscv/zba-zextw.c: Ditto. Co-authored-by: Kito Cheng Co-authored-by: Jia-Wei Chen --- gcc/config/riscv/bitmanip.md | 76 +++++++++++++++++++ gcc/config/riscv/riscv.md | 14 +++- gcc/testsuite/gcc.target/riscv/zba-adduw.c | 12 +++ .../gcc.target/riscv/zba-shNadd-01.c | 19 +++++ .../gcc.target/riscv/zba-shNadd-02.c | 19 +++++ .../gcc.target/riscv/zba-shNadd-03.c | 31 ++++++++ gcc/testsuite/gcc.target/riscv/zba-slliuw.c | 11 +++ gcc/testsuite/gcc.target/riscv/zba-zextw.c | 10 +++ 8 files changed, 188 insertions(+), 4 deletions(-) create mode 100644 gcc/config/riscv/bitmanip.md create mode 100644 gcc/testsuite/gcc.target/riscv/zba-adduw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-01.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-02.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-shNadd-03.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-slliuw.c create mode 100644 gcc/testsuite/gcc.target/riscv/zba-zextw.c diff --git a/gcc/config/riscv/bitmanip.md b/gcc/config/riscv/bitmanip.md new file mode 100644 index 00000000000..3849d21dc15 --- /dev/null +++ b/gcc/config/riscv/bitmanip.md @@ -0,0 +1,76 @@ +;; Machine description for RISC-V Bit Manipulation operations. +;; Copyright (C) 2021 Free Software Foundation, Inc. + +;; This file is part of GCC. + +;; GCC is free software; you can redistribute it and/or modify +;; it under the terms of the GNU General Public License as published by +;; the Free Software Foundation; either version 3, or (at your option) +;; any later version. + +;; GCC is distributed in the hope that it will be useful, +;; but WITHOUT ANY WARRANTY; without even the implied warranty of +;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +;; GNU General Public License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + +;; ZBA extension. + +(define_insn "*zero_extendsidi2_bitmanip" + [(set (match_operand:DI 0 "register_operand" "=r,r") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" "r,m")))] + "TARGET_64BIT && TARGET_ZBA" + "@ + zext.w\t%0,%1 + lwu\t%0,%1" + [(set_attr "type" "bitmanip,load") + (set_attr "mode" "DI")]) + +(define_insn "*shNadd" + [(set (match_operand:X 0 "register_operand" "=r") + (plus:X (ashift:X (match_operand:X 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand:X 3 "register_operand" "r")))] + "TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3)" + "sh%2add\t%0,%1,%3" + [(set_attr "type" "bitmanip") + (set_attr "mode" "")]) + +(define_insn "*shNadduw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")) + (match_operand:DI 4 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[2]) >= 1) && (INTVAL (operands[2]) <= 3) + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "sh%2add.uw\t%0,%1,%4" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*add.uw" + [(set (match_operand:DI 0 "register_operand" "=r") + (plus:DI (zero_extend:DI + (match_operand:SI 1 "register_operand" "r")) + (match_operand:DI 2 "register_operand" "r")))] + "TARGET_64BIT && TARGET_ZBA" + "add.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) + +(define_insn "*slliuw" + [(set (match_operand:DI 0 "register_operand" "=r") + (and:DI (ashift:DI (match_operand:DI 1 "register_operand" "r") + (match_operand:QI 2 "immediate_operand" "I")) + (match_operand 3 "immediate_operand" "")))] + "TARGET_64BIT && TARGET_ZBA + && (INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff" + "slli.uw\t%0,%1,%2" + [(set_attr "type" "bitmanip") + (set_attr "mode" "DI")]) diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index f88877fd596..dedfd20e5b3 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -170,7 +170,7 @@ (define_attr "type" "unknown,branch,jump,call,load,fpload,store,fpstore, mtc,mfc,const,arith,logical,shift,slt,imul,idiv,move,fmove,fadd,fmul, - fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost" + fmadd,fdiv,fcmp,fcvt,fsqrt,multi,auipc,sfb_alu,nop,ghost,bitmanip" (cond [(eq_attr "got" "load") (const_string "load") ;; If a doubleword move uses these expensive instructions, @@ -1302,11 +1302,16 @@ ;; Extension insns. -(define_insn_and_split "zero_extendsidi2" +(define_expand "zero_extendsidi2" + [(set (match_operand:DI 0 "register_operand") + (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand")))] + "TARGET_64BIT") + +(define_insn_and_split "*zero_extendsidi2_internal" [(set (match_operand:DI 0 "register_operand" "=r,r") (zero_extend:DI (match_operand:SI 1 "nonimmediate_operand" " r,m")))] - "TARGET_64BIT" + "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)" "@ # lwu\t%0,%1" @@ -2078,7 +2083,7 @@ (match_operand:QI 2 "immediate_operand" "I")) (match_operand 3 "immediate_operand" ""))) (clobber (match_scratch:DI 4 "=&r"))] - "TARGET_64BIT + "TARGET_64BIT && !TARGET_ZBA && ((INTVAL (operands[3]) >> INTVAL (operands[2])) == 0xffffffff)" "#" "&& reload_completed" @@ -2845,6 +2850,7 @@ "\t%3, %1\;\t%0, %2\;xor\t%0, %3, %0\;li\t%3, 0" [(set_attr "length" "12")]) +(include "bitmanip.md") (include "sync.md") (include "peephole.md") (include "pic.md") diff --git a/gcc/testsuite/gcc.target/riscv/zba-adduw.c b/gcc/testsuite/gcc.target/riscv/zba-adduw.c new file mode 100644 index 00000000000..cac1e849728 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zba-adduw.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zba_zbs -mabi=lp64 -O2" } */ + +int foo(int n, unsigned char *arr, unsigned y){ + int s = 0; + unsigned x = 0; + for (;x