diff mbox series

[RFC,1/8] RISC-V: Minimal support of bitmanip extension

Message ID 20210923075731.50125-2-kito.cheng@sifive.com
State Committed
Commit 149e217033f01410a9783c5cb2d020cf8334ae4c
Headers show
Series RISC-V: Bit-manipulation extension. | expand

Commit Message

Kito Cheng Sept. 23, 2021, 7:57 a.m. UTC
2021-09-23  Kito Cheng  <kito.cheng@sifive.com>

gcc/ChangeLog:

	* common/config/riscv/riscv-common.c (riscv_ext_version_table):
	Add zba, zbb, zbc and zbs.
	(riscv_ext_flag_table): Ditto.
	* config/riscv/riscv-opts.h (MASK_ZBA): New.
	(MASK_ZBB): Ditto.
	(MASK_ZBC): Ditto.
	(MASK_ZBS): Ditto.
	(TARGET_ZBA): Ditto.
	(TARGET_ZBB): Ditto.
	(TARGET_ZBC): Ditto.
	(TARGET_ZBS): Ditto.
	* config/riscv/riscv.opt (riscv_zb_subext): New.
---
 gcc/common/config/riscv/riscv-common.c | 10 ++++++++++
 gcc/config/riscv/riscv-opts.h          | 10 ++++++++++
 gcc/config/riscv/riscv.opt             |  3 +++
 3 files changed, 23 insertions(+)

Comments

Christoph Muellner Sept. 27, 2021, 11:16 a.m. UTC | #1
Hi Kito,

On Thu, Sep 23, 2021 at 9:57 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> 2021-09-23  Kito Cheng  <kito.cheng@sifive.com>
>
> gcc/ChangeLog:
>
>         * common/config/riscv/riscv-common.c (riscv_ext_version_table):
>         Add zba, zbb, zbc and zbs.
>         (riscv_ext_flag_table): Ditto.
>         * config/riscv/riscv-opts.h (MASK_ZBA): New.
>         (MASK_ZBB): Ditto.
>         (MASK_ZBC): Ditto.
>         (MASK_ZBS): Ditto.
>         (TARGET_ZBA): Ditto.
>         (TARGET_ZBB): Ditto.
>         (TARGET_ZBC): Ditto.
>         (TARGET_ZBS): Ditto.
>         * config/riscv/riscv.opt (riscv_zb_subext): New.
> ---
>  gcc/common/config/riscv/riscv-common.c | 10 ++++++++++
>  gcc/config/riscv/riscv-opts.h          | 10 ++++++++++
>  gcc/config/riscv/riscv.opt             |  3 +++
>  3 files changed, 23 insertions(+)
>
> diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
> index 10868fd417d..37b6ea80086 100644
> --- a/gcc/common/config/riscv/riscv-common.c
> +++ b/gcc/common/config/riscv/riscv-common.c
> @@ -101,6 +101,11 @@ static const struct riscv_ext_version riscv_ext_version_table[] =
>    {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
>    {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
>
> +  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
> +  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},

I think this needs another specification class (there is a
specification for the instructions and it is in public review).
Proposal: ISA_SPEC_CLASS_FROZEN_2021

BR
Christoph

> +
>    /* Terminate the list.  */
>    {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
>  };
> @@ -906,6 +911,11 @@ static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
>    {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
>    {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
>
> +  {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
> +  {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
> +  {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
> +  {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
> +
>    {NULL, NULL, 0}
>  };
>
> diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
> index f4cf6ca4b82..2efc4b80f1f 100644
> --- a/gcc/config/riscv/riscv-opts.h
> +++ b/gcc/config/riscv/riscv-opts.h
> @@ -73,4 +73,14 @@ enum stack_protector_guard {
>  #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
>  #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
>
> +#define MASK_ZBA      (1 << 0)
> +#define MASK_ZBB      (1 << 1)
> +#define MASK_ZBC      (1 << 2)
> +#define MASK_ZBS      (1 << 3)
> +
> +#define TARGET_ZBA    ((riscv_zb_subext & MASK_ZBA) != 0)
> +#define TARGET_ZBB    ((riscv_zb_subext & MASK_ZBB) != 0)
> +#define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
> +#define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
> +
>  #endif /* ! GCC_RISCV_OPTS_H */
> diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
> index 5ff85c21430..15bf89e17c2 100644
> --- a/gcc/config/riscv/riscv.opt
> +++ b/gcc/config/riscv/riscv.opt
> @@ -195,6 +195,9 @@ long riscv_stack_protector_guard_offset = 0
>  TargetVariable
>  int riscv_zi_subext
>
> +TargetVariable
> +int riscv_zb_subext
> +
>  Enum
>  Name(isa_spec_class) Type(enum riscv_isa_spec_class)
>  Supported ISA specs (for use with the -misa-spec= option):
> --
> 2.33.0
>
Kito Cheng Oct. 18, 2021, 8:48 a.m. UTC | #2
Hi Christoph:

> I think this needs another specification class (there is a
> specification for the instructions and it is in public review).
> Proposal: ISA_SPEC_CLASS_FROZEN_2021

That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
reference to which spec, so I would prefer to add a -misa-spec=2021 to
align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
RISC-V platform/profile spec has released, let keep
ISA_SPEC_CLASS_NONE :p

> BR
> Christoph
Christoph Muellner Oct. 18, 2021, 10:10 a.m. UTC | #3
On Mon, Oct 18, 2021 at 10:48 AM Kito Cheng <kito.cheng@sifive.com> wrote:
>
> Hi Christoph:
>
> > I think this needs another specification class (there is a
> > specification for the instructions and it is in public review).
> > Proposal: ISA_SPEC_CLASS_FROZEN_2021
>
> That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
> reference to which spec, so I would prefer to add a -misa-spec=2021 to
> align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
> RISC-V platform/profile spec has released, let keep
> ISA_SPEC_CLASS_NONE :p

For sure we cannot reference a spec that is not frozen yet (i.e.
platform/profile).
ISA_SPEC_CLASS_FROZEN_2021 was a proposal for all groups of ISA extensions
that have been frozen in 2021 (zb*, zk*, etc.) and will eventually be ratified.
But yes, keeping NONE until the specifications are ratified and change
the specification
class then is also possible.
Kito Cheng Oct. 18, 2021, 12:15 p.m. UTC | #4
> > That's a good point, but ISA_SPEC_CLASS_FROZEN_2021 is hard to
> > reference to which spec, so I would prefer to add a -misa-spec=2021 to
> > align platform/profile spec, and then ISA_SPEC_CLASS_2021, and before
> > RISC-V platform/profile spec has released, let keep
> > ISA_SPEC_CLASS_NONE :p
>
> For sure we cannot reference a spec that is not frozen yet (i.e.
> platform/profile).
> ISA_SPEC_CLASS_FROZEN_2021 was a proposal for all groups of ISA extensions
> that have been frozen in 2021 (zb*, zk*, etc.) and will eventually be ratified.
> But yes, keeping NONE until the specifications are ratified and change
> the specification
> class then is also possible.

I expect those specs can be ratified at the end of this year, and then
we still have a few months
to update before GCC 12 release.
diff mbox series

Patch

diff --git a/gcc/common/config/riscv/riscv-common.c b/gcc/common/config/riscv/riscv-common.c
index 10868fd417d..37b6ea80086 100644
--- a/gcc/common/config/riscv/riscv-common.c
+++ b/gcc/common/config/riscv/riscv-common.c
@@ -101,6 +101,11 @@  static const struct riscv_ext_version riscv_ext_version_table[] =
   {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0},
   {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0},
 
+  {"zba", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbb", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbc", ISA_SPEC_CLASS_NONE, 1, 0},
+  {"zbs", ISA_SPEC_CLASS_NONE, 1, 0},
+
   /* Terminate the list.  */
   {NULL, ISA_SPEC_CLASS_NONE, 0, 0}
 };
@@ -906,6 +911,11 @@  static const riscv_ext_flag_table_t riscv_ext_flag_table[] =
   {"zicsr",    &gcc_options::x_riscv_zi_subext, MASK_ZICSR},
   {"zifencei", &gcc_options::x_riscv_zi_subext, MASK_ZIFENCEI},
 
+  {"zba",    &gcc_options::x_riscv_zb_subext, MASK_ZBA},
+  {"zbb",    &gcc_options::x_riscv_zb_subext, MASK_ZBB},
+  {"zbc",    &gcc_options::x_riscv_zb_subext, MASK_ZBC},
+  {"zbs",    &gcc_options::x_riscv_zb_subext, MASK_ZBS},
+
   {NULL, NULL, 0}
 };
 
diff --git a/gcc/config/riscv/riscv-opts.h b/gcc/config/riscv/riscv-opts.h
index f4cf6ca4b82..2efc4b80f1f 100644
--- a/gcc/config/riscv/riscv-opts.h
+++ b/gcc/config/riscv/riscv-opts.h
@@ -73,4 +73,14 @@  enum stack_protector_guard {
 #define TARGET_ZICSR    ((riscv_zi_subext & MASK_ZICSR) != 0)
 #define TARGET_ZIFENCEI ((riscv_zi_subext & MASK_ZIFENCEI) != 0)
 
+#define MASK_ZBA      (1 << 0)
+#define MASK_ZBB      (1 << 1)
+#define MASK_ZBC      (1 << 2)
+#define MASK_ZBS      (1 << 3)
+
+#define TARGET_ZBA    ((riscv_zb_subext & MASK_ZBA) != 0)
+#define TARGET_ZBB    ((riscv_zb_subext & MASK_ZBB) != 0)
+#define TARGET_ZBC    ((riscv_zb_subext & MASK_ZBC) != 0)
+#define TARGET_ZBS    ((riscv_zb_subext & MASK_ZBS) != 0)
+
 #endif /* ! GCC_RISCV_OPTS_H */
diff --git a/gcc/config/riscv/riscv.opt b/gcc/config/riscv/riscv.opt
index 5ff85c21430..15bf89e17c2 100644
--- a/gcc/config/riscv/riscv.opt
+++ b/gcc/config/riscv/riscv.opt
@@ -195,6 +195,9 @@  long riscv_stack_protector_guard_offset = 0
 TargetVariable
 int riscv_zi_subext
 
+TargetVariable
+int riscv_zb_subext
+
 Enum
 Name(isa_spec_class) Type(enum riscv_isa_spec_class)
 Supported ISA specs (for use with the -misa-spec= option):