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Fri, 17 Sep 2021 05:25:13 +0000 (GMT) To: gcc-patches@gcc.gnu.org Subject: [PATCH v2 2/2] rs6000: Fold xxsel to vsel since they have same semantics Date: Fri, 17 Sep 2021 00:25:05 -0500 Message-Id: <20210917052505.2469224-3-luoxhu@linux.ibm.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210917052505.2469224-1-luoxhu@linux.ibm.com> References: <20210917052505.2469224-1-luoxhu@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-GUID: PnvoGlqKtuygqC8ISb9gQnvOI5JRUiOe X-Proofpoint-ORIG-GUID: 1R75z83Zxt5c1lxst8UP3QZ0kgLXRH32 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.182.1,Aquarius:18.0.790,Hydra:6.0.391,FMLib:17.0.607.475 definitions=2021-09-17_02,2021-09-16_01,2020-04-07_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 mlxlogscore=977 bulkscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 impostorscore=0 malwarescore=0 priorityscore=1501 spamscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2109030001 definitions=main-2109170032 X-Spam-Status: No, score=-11.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, RCVD_IN_MSPIKE_H4, RCVD_IN_MSPIKE_WL, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-Patchwork-Original-From: Xionghu Luo via Gcc-patches From: Xionghu Luo Reply-To: Xionghu Luo Cc: segher@kernel.crashing.org, Xionghu Luo , wschmidt@linux.ibm.com, linkw@gcc.gnu.org, dje.gcc@gmail.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Fold xxsel to vsel like xxperm/vperm to avoid duplicate code. gcc/ChangeLog: 2021-09-17 Xionghu Luo * config/rs6000/altivec.md: Add vsx register constraints. * config/rs6000/vsx.md (vsx_xxsel): Delete. (vsx_xxsel2): Likewise. (vsx_xxsel3): Likewise. (vsx_xxsel4): Likewise. --- gcc/config/rs6000/altivec.md | 60 +++++++++++-------- gcc/config/rs6000/vsx.md | 57 ------------------ gcc/testsuite/gcc.target/powerpc/builtins-1.c | 2 +- 3 files changed, 37 insertions(+), 82 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a3424e1a458..4b4ca2c5d17 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -684,56 +684,68 @@ (define_insn "*altivec_gev4sf" [(set_attr "type" "veccmp")]) (define_insn "altivec_vsel" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "register_operand" "=wa,v") (ior:VM (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 1 "altivec_register_operand" "v")) + (not:VM (match_operand:VM 3 "register_operand" "wa,v")) + (match_operand:VM 1 "register_operand" "wa,v")) (and:VM (match_dup 3) - (match_operand:VM 2 "altivec_register_operand" "v"))))] + (match_operand:VM 2 "register_operand" "wa,v"))))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecmove")]) + "@ + xxsel %x0,%x1,%x2,%x3 + vsel %0,%1,%2,%3" + [(set_attr "type" "vecmove") + (set_attr "isa" "")]) (define_insn "altivec_vsel2" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "register_operand" "=wa,v") (ior:VM (and:VM - (not:VM (match_operand:VM 3 "altivec_register_operand" "v")) - (match_operand:VM 1 "altivec_register_operand" "v")) + (not:VM (match_operand:VM 3 "register_operand" "wa,v")) + (match_operand:VM 1 "register_operand" "wa,v")) (and:VM - (match_operand:VM 2 "altivec_register_operand" "v") + (match_operand:VM 2 "register_operand" "wa,v") (match_dup 3))))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "vsel %0,%1,%2,%3" - [(set_attr "type" "vecmove")]) + "@ + xxsel %x0,%x1,%x2,%x3 + vsel %0,%1,%2,%3" + [(set_attr "type" "vecmove") + (set_attr "isa" "")]) (define_insn "altivec_vsel3" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "register_operand" "=wa,v") (ior:VM (and:VM - (match_operand:VM 3 "altivec_register_operand" "v") - (match_operand:VM 1 "altivec_register_operand" "v")) + (match_operand:VM 3 "register_operand" "wa,v") + (match_operand:VM 1 "register_operand" "wa,v")) (and:VM (not:VM (match_dup 3)) - (match_operand:VM 2 "altivec_register_operand" "v"))))] + (match_operand:VM 2 "register_operand" "wa,v"))))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "vsel %0,%2,%1,%3" - [(set_attr "type" "vecmove")]) + "@ + xxsel %x0,%x2,%x1,%x3 + vsel %0,%2,%1,%3" + [(set_attr "type" "vecmove") + (set_attr "isa" "")]) (define_insn "altivec_vsel4" - [(set (match_operand:VM 0 "altivec_register_operand" "=v") + [(set (match_operand:VM 0 "register_operand" "=wa,v") (ior:VM (and:VM - (match_operand:VM 1 "altivec_register_operand" "v") - (match_operand:VM 3 "altivec_register_operand" "v")) + (match_operand:VM 1 "register_operand" "wa,v") + (match_operand:VM 3 "register_operand" "wa,v")) (and:VM (not:VM (match_dup 3)) - (match_operand:VM 2 "altivec_register_operand" "v"))))] + (match_operand:VM 2 "register_operand" "wa,v"))))] "VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)" - "vsel %0,%2,%1,%3" - [(set_attr "type" "vecmove")]) + "@ + xxsel %x0,%x2,%x1,%x3 + vsel %0,%2,%1,%3" + [(set_attr "type" "vecmove") + (set_attr "isa" "")]) ;; Fused multiply add. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 601eb81e316..1d9a1eaaa54 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -2184,63 +2184,6 @@ (define_insn "*vsx_ge__p" "xvcmpgep. %x0,%x1,%x2" [(set_attr "type" "")]) -;; Vector select -(define_insn "vsx_xxsel" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 1 "vsx_register_operand" ",wa")) - (and:VSX_L - (match_dup 3) - (match_operand:VSX_L 2 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode)" - "xxsel %x0,%x1,%x2,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel2" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (match_operand:VSX_L 1 "vsx_register_operand" ",wa")) - (and:VSX_L - (match_operand:VSX_L 2 "vsx_register_operand" ",wa") - (match_dup 3))))] - "VECTOR_MEM_VSX_P (mode)" - "xxsel %x0,%x1,%x2,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel3" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (match_operand:VSX_L 3 "vsx_register_operand" ",wa") - (match_operand:VSX_L 1 "vsx_register_operand" ",wa")) - (and:VSX_L - (not:VSX_L (match_dup 3)) - (match_operand:VSX_L 2 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode)" - "xxsel %x0,%x2,%x1,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - -(define_insn "vsx_xxsel4" - [(set (match_operand:VSX_L 0 "vsx_register_operand" "=,?wa") - (ior:VSX_L - (and:VSX_L - (match_operand:VSX_L 1 "vsx_register_operand" ",wa") - (match_operand:VSX_L 3 "vsx_register_operand" ",wa")) - (and:VSX_L - (not:VSX_L (match_dup 3)) - (match_operand:VSX_L 2 "vsx_register_operand" ",wa"))))] - "VECTOR_MEM_VSX_P (mode)" - "xxsel %x0,%x2,%x1,%x3" - [(set_attr "type" "vecmove") - (set_attr "isa" "")]) - ;; Copy sign (define_insn "vsx_copysign3" [(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa") diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c index 83aed5a5141..3ec1024a955 100644 --- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c +++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c @@ -326,7 +326,7 @@ int main () /* { dg-final { scan-assembler-times {\mvpkudus\M} 1 } } */ /* { dg-final { scan-assembler-times "vperm" 4 } } */ /* { dg-final { scan-assembler-times "xvrdpi" 2 } } */ -/* { dg-final { scan-assembler-times "xxsel" 10 } } */ +/* { dg-final { scan-assembler-times "xxsel" 5 } } */ /* { dg-final { scan-assembler-times "xxlxor" 6 } } */ /* { dg-final { scan-assembler-times "divd" 8 { target lp64 } } } */ /* { dg-final { scan-assembler-times "divdu" 2 { target lp64 } } } */