@@ -684,56 +684,68 @@ (define_insn "*altivec_gev4sf"
[(set_attr "type" "veccmp")])
(define_insn "altivec_vsel<mode>"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (not:VM (match_operand:VM 3 "altivec_register_operand" "v"))
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (not:VM (match_operand:VM 3 "register_operand" "wa,v"))
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
(match_dup 3)
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%1,%2,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x1,%x2,%x3
+ vsel %0,%1,%2,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>2"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (not:VM (match_operand:VM 3 "altivec_register_operand" "v"))
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (not:VM (match_operand:VM 3 "register_operand" "wa,v"))
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
- (match_operand:VM 2 "altivec_register_operand" "v")
+ (match_operand:VM 2 "register_operand" "wa,v")
(match_dup 3))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%1,%2,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x1,%x2,%x3
+ vsel %0,%1,%2,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>3"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (match_operand:VM 3 "altivec_register_operand" "v")
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (match_operand:VM 3 "register_operand" "wa,v")
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
(not:VM (match_dup 3))
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%2,%1,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x2,%x1,%x3
+ vsel %0,%2,%1,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>4"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (match_operand:VM 1 "altivec_register_operand" "v")
- (match_operand:VM 3 "altivec_register_operand" "v"))
+ (match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 3 "register_operand" "wa,v"))
(and:VM
(not:VM (match_dup 3))
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%2,%1,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x2,%x1,%x3
+ vsel %0,%2,%1,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
;; Fused multiply add.
@@ -2184,63 +2184,6 @@ (define_insn "*vsx_ge_<mode>_p"
"xvcmpge<sd>p. %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
-;; Vector select
-(define_insn "vsx_xxsel<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (match_dup 3)
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>2"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
- (match_dup 3))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>3"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (not:VSX_L (match_dup 3))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x2,%x1,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>4"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (not:VSX_L (match_dup 3))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x2,%x1,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
;; Copy sign
(define_insn "vsx_copysign<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
@@ -326,7 +326,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mvpkudus\M} 1 } } */
/* { dg-final { scan-assembler-times "vperm" 4 } } */
/* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 10 } } */
+/* { dg-final { scan-assembler-times "xxsel" 5 } } */
/* { dg-final { scan-assembler-times "xxlxor" 6 } } */
/* { dg-final { scan-assembler-times "divd" 8 { target lp64 } } } */
/* { dg-final { scan-assembler-times "divdu" 2 { target lp64 } } } */