From patchwork Wed Sep 15 09:36:07 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Cederman X-Patchwork-Id: 45020 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 580903857C74 for ; Wed, 15 Sep 2021 09:37:03 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from bin-mail-out-05.binero.net (bin-mail-out-05.binero.net [195.74.38.228]) by sourceware.org (Postfix) with ESMTPS id DED0D3858407 for ; Wed, 15 Sep 2021 09:36:18 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org DED0D3858407 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=gaisler.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=gaisler.com X-Halon-ID: 6049cd78-1608-11ec-8aa7-005056917f90 Authorized-sender: cederman@gaisler.com Received: from cederman.got.gaisler.com (h-98-128-223-123.na.cust.bahnhof.se [98.128.223.123]) by bin-vsp-out-02.atm.binero.net (Halon) with ESMTPA id 6049cd78-1608-11ec-8aa7-005056917f90; Wed, 15 Sep 2021 11:36:17 +0200 (CEST) From: Daniel Cederman To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/4] sparc: Treat more instructions as load or store in errata workarounds Date: Wed, 15 Sep 2021 11:36:07 +0200 Message-Id: <20210915093610.3112669-3-cederman@gaisler.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210915093610.3112669-1-cederman@gaisler.com> References: <20210915093610.3112669-1-cederman@gaisler.com> MIME-Version: 1.0 X-Spam-Status: No, score=-13.7 required=5.0 tests=BAYES_00, GIT_PATCH_0, KAM_DMARC_STATUS, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ebotcazou@libertysurf.fr Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Check the attribute of instruction to determine if it performs a store or load operation. This more generic approach sees the last instruction in the GOTdata_op model as a potential load and treats the memory barrier as a potential store instruction. gcc/ChangeLog: * config/sparc/sparc.c (store_insn_p): Add predicate for store attributes. (load_insn_p): Add predicate for load attributes. (sparc_do_work_around_errata): Use new predicates. --- gcc/config/sparc/sparc.c | 37 +++++++++++++++++++++++++++++-------- 1 file changed, 29 insertions(+), 8 deletions(-) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index d5a0ff7d4ea..fa78e0dc739 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1045,6 +1045,31 @@ atomic_insn_for_leon3_p (rtx_insn *insn) } } +/* True if INSN is a store instruction. */ + +static bool +store_insn_p (rtx_insn *insn) +{ + if (GET_CODE (PATTERN (insn)) != SET) + return false; + + return (get_attr_type (insn) == TYPE_STORE) + || (get_attr_type (insn) == TYPE_FPSTORE); +} + +/* True if INSN is a load instruction. */ + +static bool +load_insn_p (rtx_insn *insn) +{ + if (GET_CODE (PATTERN (insn)) != SET) + return false; + + return (get_attr_type (insn) == TYPE_LOAD) + || (get_attr_type (insn) == TYPE_SLOAD) + || (get_attr_type (insn) == TYPE_FPLOAD); +} + /* We use a machine specific pass to enable workarounds for errata. We need to have the (essentially) final form of the insn stream in order @@ -1105,9 +1130,7 @@ sparc_do_work_around_errata (void) instruction at branch target. */ if (sparc_fix_ut700 && NONJUMP_INSN_P (insn) - && (set = single_set (insn)) != NULL_RTX - && mem_ref (SET_SRC (set)) - && REG_P (SET_DEST (set))) + && load_insn_p (insn)) { if (jump && jump_to_label_p (jump)) { @@ -1212,7 +1235,7 @@ sparc_do_work_around_errata (void) if (sparc_fix_b2bst && NONJUMP_INSN_P (insn) && (set = single_set (insn)) != NULL_RTX - && MEM_P (SET_DEST (set))) + && store_insn_p (insn)) { /* Sequence B begins with a double-word store. */ bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8; @@ -1245,8 +1268,7 @@ sparc_do_work_around_errata (void) if (seq_b) { /* Add NOP if followed by a store. */ - if ((set = single_set (after)) != NULL_RTX - && MEM_P (SET_DEST (set))) + if (store_insn_p (after)) insert_nop = true; /* Otherwise it is ok. */ @@ -1268,8 +1290,7 @@ sparc_do_work_around_errata (void) /* Add NOP if third instruction is a store. */ if (i == 1 - && (set = single_set (after)) != NULL_RTX - && MEM_P (SET_DEST (set))) + && store_insn_p (after)) insert_nop = true; } }