From patchwork Fri Dec 17 17:36:30 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Segher Boessenkool X-Patchwork-Id: 49059 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 9D1303857C4C for ; Fri, 17 Dec 2021 17:36:59 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from gcc1-power7.osuosl.org (gcc1-power7.osuosl.org [140.211.15.137]) by sourceware.org (Postfix) with ESMTP id 513513858412 for ; Fri, 17 Dec 2021 17:36:40 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 513513858412 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=kernel.crashing.org Authentication-Results: sourceware.org; spf=none smtp.mailfrom=gcc1-power7.osuosl.org Received: by gcc1-power7.osuosl.org (Postfix, from userid 10019) id 1132312408CD; Fri, 17 Dec 2021 17:36:38 +0000 (UTC) From: Segher Boessenkool To: gcc-patches@gcc.gnu.org Subject: [PATCH 1/2] rs6000: Redo darn (PR103624) Date: Fri, 17 Dec 2021 17:36:30 +0000 Message-Id: <13977b80c6a1deb0dc048f36f262cb3ec9c4d48c.1639760570.git.segher@kernel.crashing.org> X-Mailer: git-send-email 1.8.3.1 X-Spam-Status: No, score=-12.9 required=5.0 tests=BAYES_00, GIT_PATCH_0, HEADER_FROM_DIFFERENT_DOMAINS, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, SPF_HELO_NONE, SPF_NONE, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: wschmidt@linux.ibm.com, Segher Boessenkool , dje.gcc@gmail.com Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" The builtins now all return "long". The patterns have :GPR as the output mode, so they can be 32-bit as well (the instruction makes sense in 32 bit just fine). The builtins expand to the DImode version normally, but to the SImode if {32bit} is true. 2021-12-17 Segher Boessenkool PR target/103624 * config/rs6000/rs6000-builtins.def (__builtin_darn): Expand to darn_64_di. Add {32bit} attribute. Return long. (__builtin_darn_32): Expand to darn_32_di. Add {32bit} attribute. Return long. (__builtin_darn_raw): Expand to darn_raw_di. Add {32bit} attribute. Return long. * config/rs6000/rs6000-call.c (rs6000_expand_builtin): Expand the darn builtins to the _si variants for -m32. * config/rs6000/rs6000.md (UNSPECV_DARN_32, UNSPECV_DARN_RAW): Delete. (UNSPECV_DARN): Update comment. (darn_32, darn_raw, darn): Delete. (darn_32_, darn_64_, darn_raw_ for GPR): New. (@darn for GPR): New. --- gcc/config/rs6000/rs6000-builtins.def | 12 ++++----- gcc/config/rs6000/rs6000-call.c | 6 +++++ gcc/config/rs6000/rs6000.md | 47 +++++++++++++++++++++-------------- 3 files changed, 40 insertions(+), 25 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtins.def b/gcc/config/rs6000/rs6000-builtins.def index 45ce160bd421..3ad5a135eaec 100644 --- a/gcc/config/rs6000/rs6000-builtins.def +++ b/gcc/config/rs6000/rs6000-builtins.def @@ -2798,14 +2798,14 @@ ; Miscellaneous P9 functions [power9] - signed long long __builtin_darn (); - DARN darn {} + signed long __builtin_darn (); + DARN darn_64_di {32bit} - signed int __builtin_darn_32 (); - DARN_32 darn_32 {} + signed long __builtin_darn_32 (); + DARN_32 darn_32_di {32bit} - signed long long __builtin_darn_raw (); - DARN_RAW darn_raw {} + signed long __builtin_darn_raw (); + DARN_RAW darn_raw_di {32bit} const signed int __builtin_dtstsfi_eq_dd (const int<6>, _Decimal64); TSTSFI_EQ_DD dfptstsfi_eq_dd {} diff --git a/gcc/config/rs6000/rs6000-call.c b/gcc/config/rs6000/rs6000-call.c index b98f4a4c97f7..cc55174c6b72 100644 --- a/gcc/config/rs6000/rs6000-call.c +++ b/gcc/config/rs6000/rs6000-call.c @@ -5631,6 +5631,12 @@ rs6000_expand_builtin (tree exp, rtx target, rtx /* subtarget */, icode = CODE_FOR_rs6000_mftb_si; else if (fcode == RS6000_BIF_BPERMD) icode = CODE_FOR_bpermd_si; + else if (fcode == RS6000_BIF_DARN) + icode = CODE_FOR_darn_64_si; + else if (fcode == RS6000_BIF_DARN_32) + icode = CODE_FOR_darn_32_si; + else if (fcode == RS6000_BIF_DARN_RAW) + icode = CODE_FOR_darn_raw_si; else gcc_unreachable (); } diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4122acb98cfd..9be484c7cf83 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -172,9 +172,7 @@ (define_c_enum "unspecv" UNSPECV_EH_RR ; eh_reg_restore UNSPECV_ISYNC ; isync instruction UNSPECV_MFTB ; move from time base - UNSPECV_DARN ; darn 1 (deliver a random number) - UNSPECV_DARN_32 ; darn 2 - UNSPECV_DARN_RAW ; darn 0 + UNSPECV_DARN ; darn (deliver a random number) UNSPECV_NLGR ; non-local goto receiver UNSPECV_MFFS ; Move from FPSCR UNSPECV_MFFSL ; Move from FPSCR light instruction version @@ -15065,25 +15063,36 @@ (define_insn "*cmp_hw" ;; Miscellaneous ISA 3.0 (power9) instructions -(define_insn "darn_32" - [(set (match_operand:SI 0 "register_operand" "=r") - (unspec_volatile:SI [(const_int 0)] UNSPECV_DARN_32))] +(define_expand "darn_32_" + [(use (match_operand:GPR 0 "register_operand"))] "TARGET_P9_MISC" - "darn %0,0" - [(set_attr "type" "integer")]) +{ + emit_insn (gen_darn (mode, operands[0], const0_rtx)); + DONE; +}) -(define_insn "darn_raw" - [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN_RAW))] - "TARGET_P9_MISC && TARGET_64BIT" - "darn %0,2" - [(set_attr "type" "integer")]) +(define_expand "darn_64_" + [(use (match_operand:GPR 0 "register_operand"))] + "TARGET_P9_MISC" +{ + emit_insn (gen_darn (mode, operands[0], const1_rtx)); + DONE; +}) -(define_insn "darn" - [(set (match_operand:DI 0 "register_operand" "=r") - (unspec_volatile:DI [(const_int 0)] UNSPECV_DARN))] - "TARGET_P9_MISC && TARGET_64BIT" - "darn %0,1" +(define_expand "darn_raw_" + [(use (match_operand:GPR 0 "register_operand"))] + "TARGET_P9_MISC" +{ + emit_insn (gen_darn (mode, operands[0], const2_rtx)); + DONE; +}) + +(define_insn "@darn" + [(set (match_operand:GPR 0 "register_operand" "=r") + (unspec_volatile:GPR [(match_operand 1 "const_int_operand" "n")] + UNSPECV_DARN))] + "TARGET_P9_MISC" + "darn %0,%1" [(set_attr "type" "integer")]) ;; Test byte within range.