From patchwork Wed May 18 17:30:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Roger Sayle X-Patchwork-Id: 54175 Return-Path: X-Original-To: patchwork@sourceware.org Delivered-To: patchwork@sourceware.org Received: from server2.sourceware.org (localhost [IPv6:::1]) by sourceware.org (Postfix) with ESMTP id 71783385480D for ; Wed, 18 May 2022 17:34:31 +0000 (GMT) X-Original-To: gcc-patches@gcc.gnu.org Delivered-To: gcc-patches@gcc.gnu.org Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 1C1493856DF6 for ; Wed, 18 May 2022 17:30:39 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 1C1493856DF6 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=T9M1RTeCuFjN7fVKdsjhLUzlNT8CMr5clVP3m0zU+NA=; b=QmcDWeA6bzLGXcXyb6FowsJ8j7 9IoqzExtet0mJfvIGEUnovjfUNGEl8E1c4Cs1WH7VskBVwbhTZPWbZx6Qe0eH5ha3hwEFfZR1Kwtb b6C4iGy6T33a5lR6C9BvBig6zrKFOsM59n+kfvM/Mo4i1dKhN2DrDjRUhQMrD8Cd5OvA9l4zCtZ8m Qhd30P/V5GC03aC0WbqpTdq4tmcgK2Q6wA9M3MrdkoFHwSP9pz+SHuVgIYVw6f7HI3hgm5FfH4AnS F5MTG04vREGuQRPZ67t2Qk/gGvz9UbpypKBjq110QgBxHP+zU75hbuobGWeBhFaDlfWjnjo9hjihP PmPUizbg==; Received: from [185.62.158.67] (port=52982 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nrNVO-0001uk-JN; Wed, 18 May 2022 13:30:38 -0400 From: "Roger Sayle" To: Subject: [x86 PATCH] Some additional ix86_rtx_costs clean-ups: NEG, AND and pandn. Date: Wed, 18 May 2022 18:30:37 +0100 Message-ID: <065001d86adc$fd6f7880$f84e6980$@nextmovesoftware.com> MIME-Version: 1.0 X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adhq3ErkuBjs2JnvS5Wv9FvGp6Icpw== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: gcc-patches-bounces+patchwork=sourceware.org@gcc.gnu.org Sender: "Gcc-patches" Hi Uros, Very many thanks for the speedy review and approval of my ix86_rtx_costs patch to correct the cost of multi-word multiplications. In the same spirit, this patch tidies up a few additional nits I noticed while there: Multi-word NOT requires two operations, but multi-word NEG requires three operations. Using SSE, vector NOT requires a pxor with -1, but AND of NOT is cheap thanks to the existence of pandn. There's also some legacy (aka incorrect) logic explicitly testing for DImode [independently of TARGET_64BIT] in determining the cost of logic operations that's not required. There should be no behavioural changes from this patch (as confirmed by testing) but hopefully vectorization and other middle-end passes can now rely on more sensible "cost" estimates. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2022-05-18 Roger Sayle gcc/ChangeLog * config/i386/i386.cc (ix86_rtx_costs): Split AND from XOR/IOR. Multi-word binary logic operations require two instructions. For vector integer modes, AND with a NOT operand requires only a single instruction (pandn). [NOT]: Vector integer NOT requires more than 1 instruction (pxor). [NEG]: Multi-word negation requires 3 instructions. Thanks in advance, Roger diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc index 86752a6..1701244 100644 --- a/gcc/config/i386/i386.cc +++ b/gcc/config/i386/i386.cc @@ -20744,26 +20744,67 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, } /* FALLTHRU */ - case AND: case IOR: case XOR: if (GET_MODE_CLASS (mode) == MODE_INT && GET_MODE_SIZE (mode) > UNITS_PER_WORD) { - *total = (cost->add * 2 - + (rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed) - << (GET_MODE (XEXP (x, 0)) != DImode)) - + (rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed) - << (GET_MODE (XEXP (x, 1)) != DImode))); + *total = cost->add * 2 + + rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed); + return true; + } + else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + *total = ix86_vec_cost (mode, cost->sse_op); + else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + *total = cost->add * 2; + else + *total = cost->add; + return false; + + case AND: + if (GET_MODE_CLASS (mode) == MODE_INT + && GET_MODE_SIZE (mode) > UNITS_PER_WORD) + { + *total = cost->add * 2 + + rtx_cost (XEXP (x, 0), mode, outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, outer_code, opno, speed); return true; } - else if (code == AND - && address_no_seg_operand (x, mode)) + else if (address_no_seg_operand (x, mode)) { *total = cost->lea; return true; } - /* FALLTHRU */ + else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + { + /* pandn is a single instruction. */ + if (GET_CODE (XEXP (x, 0)) == NOT) + { + *total = ix86_vec_cost (mode, cost->sse_op) + + rtx_cost (XEXP (XEXP (x, 0), 0), mode, + outer_code, opno, speed) + + rtx_cost (XEXP (x, 1), mode, + outer_code, opno, speed); + return true; + } + *total = ix86_vec_cost (mode, cost->sse_op); + } + else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + *total = cost->add * 2; + else + *total = cost->add; + return false; + + case NOT: + if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + // vnot is pxor -1. + *total = ix86_vec_cost (mode, cost->sse_op) + 1; + else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) + *total = cost->add * 2; + else + *total = cost->add; + return false; case NEG: if (SSE_FLOAT_MODE_SSEMATH_OR_HF_P (mode)) @@ -20781,13 +20822,10 @@ ix86_rtx_costs (rtx x, machine_mode mode, int outer_code_i, int opno, *total = ix86_vec_cost (mode, cost->sse_op); return false; } - /* FALLTHRU */ - - case NOT: - if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) + else if (GET_MODE_CLASS (mode) == MODE_VECTOR_INT) *total = ix86_vec_cost (mode, cost->sse_op); else if (GET_MODE_SIZE (mode) > UNITS_PER_WORD) - *total = cost->add * 2; + *total = cost->add * 3; else *total = cost->add; return false;